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Prototypes, Platforms, and Emulation: Understanding Pros and Cons

Comments(4)Filed under: Industry Insights, RTL Compiler, C-to-Silicon Complier, Conformal

Claims and confusion abound in the marketplace when it comes to three technologies that are widely used for system validation – virtual platforms, emulation, and FPGA prototyping. This posting is an attempt to shed some light by looking at the pros and cons of each.

Perspectives given here come from a recent discussion with Ran Avinun, marketing group director for system design and verification at Cadence. Ran just published an article in Chip Design magazine that addresses some misconceptions about FPGA prototyping and processor-based emulation. Basically, he refutes claims that “big-box” emulation is too expensive and no longer necessary, and notes some of the often-overlooked costs of FPGA prototypes.

Let’s start at the front of the design cycle, though, with virtual platforms, which are widely used to develop and debug embedded software and hardware/software architectures. What are the pros? Low replicant cost, extremely fast speeds (10-1000 MHz), and executable files that can be easily distributed -- all of which are extremely appealing to software developers. One potential drawback is bring-up time of weeks to months for the first platform, unless your models are really abstract. Another is accuracy; although virtual platforms are great for software developers and architects, they generally aren’t accurate enough to handle much that involves hardware or timing.

Availability of models has been a major limitation for virtual platforms. Many legacy models are available on RTL only. Many of the virtual platform providers used to charge their customers for model creation through standard products or services. Ran believes a transition is currently underway and that over time, virtual platform providers will focus more on tool development and less on custom model creation.

Emulation brings in the accuracy that’s missing in virtual platforms. Emulation is cycle-accurate, and runs at the register-transfer level. Yet it’s fast enough – around 1 to 1.5 MHz – to do system validation and low-level software validation, with full signal visibility for debugging. Bring-up time is very short compared to FPGA prototypes – a matter of days. Turnaround time could be as short as minutes to hours. One emulator supports a large number of users. Emulation has great scalability and can support full system validation for the largest designs in the market.

The main downside to emulation is the initial cost for a full system mid-size configuration. As Ran points out, however, what you really need to look at is total cost of ownership. Emulation, with its fast bring-up times, requires fewer personnel to manage than FPGA prototypes. For example, Ran said, an FPGA prototype might require 6-8 people for bringup and maintenance, while an emulator might require one person to support a number of projects.

Advantages of FPGA prototypes include low initial cost, high performance (5-200 MHz), and a small footprint. The high speeds allow software application-level development and debugging, although not too early in the design cycle, because you have to be far enough along to have your RTL and bring up the prototype environment.

One disadvantage is an unpredictable bringup time that could vary from a few weeks to a few months. The larger the design, the longer it takes to bring up the FPGA prototyping platform. Another is debugging. FPGA prototypes running at speed don’t provide full signal visibility. You may need to stop the session and upload the data to a simulator for debugging. It could take a long time to reproduce the problem in such a case.

Some design teams use emulation to find most of the bugs, and then turn to FPGA prototypes when the design is more stable. And that brings out an important point – the three technologies described here are complementary. No one technology replaces any of the others; each has its advantages and drawbacks.

“For a long time, I think people will use a combination of virtual platforms, emulation, and FPGA prototyping,” Ran said. “Early in the design they’ll use virtual platforms, then they’ll move into emulation, and in the last phase they’ll use FPGA prototyping.” Cadence does not have an FPGA prototyping offer today, but Ran said “we continue to assess the situation. We recognize there is value there. We also recognize some difficulties and challenges.”

Richard Goering

Comments(4)

By Keith Felton on June 3, 2009
Cadence just announced FPGA System Planner, an FPGA-PCB co-design solution which delivers automated placement-aware FPGA pin I/O assignment synthesis to reduce risk and shorten the time to design-in complex FPGAs.  Now design teams have access to a solution that significantly reduces the bring-up time of the FPGA prototype.  For more information visit:
www.cadence.com/.../feature.aspx

By Lauro Rizzatti on June 3, 2009
Richard, I am not aware of any commercial FPGA protyping solution that addresses designs of tens of millions of ASIC gates (for which you may need 20 or more FPGA's) but such designs are more and more popular. The latest ASIC in the top-of-the-line camcorder of a famous company reaches now 40 million ASIC gates.
The statement that you need all three solutions may not be applicable in such instances, but you may think of an emulation solution that can act as an FPGA protoype for very large designs (possibly without the drawback of the latter).

By rgoering on June 3, 2009
Lauro, I don't mean to imply that virtual platforms, emulators and FPGA prototypes are all needed for each and every design -- just that they're complementary. Your point about the capacity limits of FPGA prototypes is well taken and is another good argument for emulation solutions.

By Hemant Shah on June 3, 2009
To get to a system that can be used to debug an ASIC prototype board using FPGAs, following four things must happen:
1) Development and verification of RTL Code
2) For developing a prototype using FPGAs on board, partitioning of RTL code into chunks that can fit into selected set of FPGAs
3) Putting FPGAs on board
4) Debugging the prototype board
Cadence FPGA System planner helps with #3. It is naïve to think of this step (#3) as only assigning pins to FPGAs and assume that it takes no time at all to place and route these FPGAs on the board. Reality is that this can take weeks to months and anything that can be done to shorten  - a) Time to assign pins to FPGAs and b) time to route these FPGAs on board – will shorten the time to “bring-up” ASIC prototype using FPGAs on board significantly.
Qualcomm presented a paper at CDNLive! SV 2008 that showcased the value they derived by using the technology in Cadence FPGA System Planner – designing 5 boards with 48 FPGAs in half the time compared to designing 19 FPGAs on one board with manual pin assignment approach. Assuming that the challenge to design FPGAs grows linearly with the increase in # of FPGAs on a board (in reality the challenge increases non-linerarly), if you do the math, you will find QCOM achieved 80% reduction in time to design in 48 FPGAs on 5 boards compared to manual methods!  

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