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Meeting the Embedded Software Challenge

Comments(0)Filed under: Industry Insights, RTOS, incisive software extensions, ESDT, ITRS, ISX

As software development costs accelerate, and current tools and methodologies run out of steam, the question of how the EDA community should respond has become very timely. It’s time for an industry-wide discussion, and it should start with a look at the challenges. As software development costs accelerate, and current tools and methodologies run out of steam, the question of how the EDA community should respond has become very timely. It’s time for an industry-wide discussion, and it should start with a look at the challenges.

Several sources confirm that software development costs are rapidly outpacing hardware development costs. International Business Strategies (IBS), for example, has looked at software versus hardware development costs at various process nodes. At 65 nm, according to IBS data, semiconductor companies will spend more on software development than hardware, and by 22 nm, software will account for three-quarters of the total development cost.

I asked Handel Jones, IBS president, why. It’s because customer expectations are changing, he said. Previously, semiconductor vendors provided only driver software, but now they’re expected to supply full “platform” solutions, including an operating system and applications software. As a result, semiconductor vendors are either building up their own software development teams or relying on outsourcing. They’re having a lot of challenges. “But every time there’s a problem,” Jones noted, “there’s an opportunity.”

Another data point comes from the International Technology Roadmap for Semiconductors (ITRS), which runs a “cost chart” in its annual Design report projecting total hardware and software engineering costs for a typical high-end SoC. The change is stunning. In the year 2000, the cost chart showed $21 million for hardware engineering and tool costs and $2 million for software engineering and tool costs. In 2007, following the introduction of very large block reuse, the chart shows hardware costs declining to $15M, but software costs soared to $24M. The projection for 2009 is $16M for hardware and $30M for software. For 2012, it’s $26M for hardware and $79M for software.

The ITRS cost chart projects that software development costs will drop in 2013, and reach rough parity with hardware costs, with the advent of “manycore development tools” (and who will provide those is an interesting question). Still, it appears that the growing cost of SoC development is mostly attributable to the embedded software challenge. The ITRS 2007 report stated that “software aspects of IC design can now account for 80% or more of embedded systems development cost.”

To date, far more expense and effort has gone into hardware development than software development. Methodologies for hardware design and verification are well defined, and EDA tools have provided orders-of-magnitude increases in productivity. Software development and verification methodologies are much more “ad hoc” and are generally lacking in sophisticated tools.

I always found it ironic that there are many more software developers than hardware engineers, yet the embedded software tool development (ESDT) business is far smaller than EDA. That’s because average selling prices are much lower in ESDT. Most software development tools are open-source, or free, or are inexpensive utilities associated with a commercial real-time operating system (RTOS). Not surprisingly, this has not been an attractive market for EDA vendors.

With the rapidly rising costs of embedded software development, and the parallel programming challenges resulting from multicore and manycore platforms, things are bound to change. New tools and methodologies will arrive. Companies that want to remain competitive will make the needed investments to improve software quality and boost time-to-market.

EDA vendors can help wherever hardware expertise is required – and it will be, especially in the multicore world. Jones envisions system-level tools that do hardware/software partitioning, analyze architectural tradeoffs, and let software and hardware development and debug run in parallel.

Some parts of that flow already exist. Virtual platforms, for instance, let developers run software on models of system hardware. Hardware/software co-verification is available in various forms. One interesting approach is Cadence Incisive Software Extensions, which gives the verification testbench access to software executing on processor models. It can bring the benefits of pseudo-random test generation, verification planning, and coverage metrics to software verification.

I’ll leave it to future blogs (by myself and others) to provide more thoughts and details about how the EDA community – including vendors, researchers, and academics – can respond to the software development challenge. ESDT providers, silicon IP companies, and customers need to come to the table as well. It’s looking like an “all hands on deck” situation as we head into the next decade.

Richard Goering

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