With no standard way to represent power consumption for silicon IP, early IC power estimation can be difficult. But help may be on the way, as the SPIRIT Consortium and its members, including Cadence, discuss possible approaches to IP power modeling.
I first became aware of this problem at a seminar held by Cadence on the Encounter Digital Implementation System 8.1. During a discussion about chip planning, an audience member noted that there is no standard way for hard IP providers to represent power data. Thus, he noted, one provider might use a worst-case number derived from a static analysis, while another uses a best-case number from simulation. This makes it difficult to run a meaningful chip estimation that includes power.
For more insight into the problem, I talked to Thad McCracken, product engineer for chip planning solutions at Cadence. He noted that it’s somewhat problematic to give a power consumption number for a given piece of IP. You can say the IP consumes 145 milliwatts, but what is that statement based on? Actual power consumption depends on many factors, including technology node, activity level, clock rates, and selection of low or high voltage threshold cells. It’s also impacted by voltage and temperature – and we may not know whether the IP provider assumed best case, worst case, or something in between.
Moreover, Thad noted, embedded IP increasingly comes with low-power features such as voltage domains. What information is conveyed about those domains, when they shut off, and what voltage levels they run? A processor core probably has different operating modes, such as active, idle and sleep. To get a good power estimation, you have to know what the processor is doing at any given time.
“If one vendor characterizes power consumption in IP with one set of assumptions, and another vendor assumes a different set of conditions, and you put all those numbers together in an estimation context, it’s difficult to know whether your total chip power estimate is realistic,” Thad said.
The folks over at the SPIRIT Consortium are aware of the problem and are discussing ways to resolve it. SPIRIT provides IP-XACT, an XML-based metadata specification that describes many aspects of IP. Now, SPIRIT is considering ways in which IP-XACT can be leveraged to describe power.
Gary Delp, SPIRIT technical director, said that a solution to the power modeling issue will have three aspects: a common vocabulary, a data representation, and a set of modeling assumptions that come with the data representation. He noted three possible approaches that could be taken with IP-XACT to help provide consistent power information:
Using “tags” that can identify which tools were used to analyze a given piece of IP, thus helping describe the methodology behind a power number.
- Providing power intent information. This would include representation of power domains, as well as control signals provided or required for retention and isolation. This information could be translated into the CPF or UPF power formats.
- Conveying power characterization based on a “vocabulary” that has been agreed upon for power domains, supply states, and power states. (One issue here is getting agreement on the metrics in which power consumption is described).
Right now, it’s all still in the discussion phase, but Gary said he’s hoping to have a clearer view of what might be possible by the July Design Automation Conference. The intent is to provide a standard way to convey information, not to enforce a standard methodology.
Gary is also a distinguished engineer at LSI Logic, which has a stake in the discussion. “Power is very important to our customers,” he said. “We want to be able to give an accurate view as early as possible. If we over-estimate power, we’re making it [IP] more expensive. If we under-estimate, it’s even worse.” SPIRIT, he said, is “trying to get a language we can use to convey conclusions from one group to another.”