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<?xml-stylesheet type="text/xsl" href="http://www.cadence.com/Community/utility/FeedStylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Tips on Using “vhdlsync” With e+Mixed HDL Simulation</title><link>http://www.cadence.com/Community/blogs/fv/archive/2009/06/11/tips-on-using-vhdlsync-with-e-mixed-hdl-simulation.aspx</link><description>[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous &amp;ldquo;vhdlsync&amp;rdquo; switch] As users with mixed VHDL and Verilog environments know, even in this day &amp;amp; age mixed HDL simulation</description><dc:language>en</dc:language><generator>CommunityServer 2007.1 (Build: 20917.1142)</generator></channel></rss>