Functional Verification - All Comments

You're welcome! ...

Anonymous — Fri, 27 Jan 2012 19:22:12 GMT

You're welcome!

Yes, please do file the two separate support tickets as tickets from the outside world/customers generally get a higher priority, and given the diversity of the issues there is a probability two different people will be assigned the respective issues (i.e. a Technical Writer would update the doc, whereas an R&D person would likely review the search issue.)

Thanks for your quic ...

Anonymous — Fri, 27 Jan 2012 08:36:53 GMT

Thanks for your quick answer.

Do you think it's better to open a support ticket about the Interface Verification Primer?

Actually, that would be two tickets: one asking for an update, the other about the "findability" of that document (e.g., I don't get a search hit with either the known full title nor the file name on support.cadence.com).

Thanks for your comm ...

Anonymous — Thu, 26 Jan 2012 23:48:26 GMT

Thanks for your comment, Colin!

Indeed, each engineer has their own preferences for getting product information in general. And as you note reuse of code examples is particularly well supported by written docs vs. video. Conversely, well executed video demos can really highlight use models / processes that can be challenging to capture in words and static screen shots. Hence, we try to strike a balance, and we assure you that we are not giving up on written documentation – we are just extending the ways we provide information.

As for the doc refresh cycle: thank you for pointing out area(s) that need updating! Given the volume of documentation we support, we appreciate user feedback on areas that are fine as-is, and those that need a refresh (beyond the obvious changes called for when tool enhancements are introduced).

Hi Anu, I complet ...

Anonymous — Thu, 26 Jan 2012 18:52:48 GMT

Hi Anu,

I completely agree that smartphones and tablets are a huge, if not #1 driver of semiconductor consumption in general, and will outpace "traditional" laptops and desktop computers. However, since so much has already been written on that, I wanted to highlight new TV tech as an equally impressive growth driver.

Thanks for the note on the upcoming DVCon tutorial -- I hope you can attend!

Joe

I, for one, prefer w ...

Anonymous — Thu, 26 Jan 2012 18:25:26 GMT

I, for one, prefer written documentation like reference manuals *every single

time* over videos or webinars. I can read them at my own leisure

and speed, the amount of marketing fluff is low, I don't harrass

colleagues with the audio (nor do I have to search for headphones),

can grep through them and can copy code.

Also, I don't need to find a way to watch them in the first place -

my workstation has a rather oldish Linux on it, mostly because EDA

vendors are so conservative with what versions they support.

You guys actually *have* well-written docs like

verif_docs/interface_verif_primer1_5.pdf (pretty hard to find

though!), but those best documents are from 2006 and could use an

update.

Hi Joe, Also whil ...

Anonymous — Wed, 18 Jan 2012 01:44:36 GMT

Hi Joe,

Also while following the EDA industry trends I have understood, that from the Chip design and innovation side, focus would be more on chips being used in smartphones and tablets as compared to laptops and desktops in the last 5 years. That is one of the reasons Qualcomm is doing good. Any comments ?

Further I read the abstract of the tutorial that you are hosting. Great going with collaboration with Nextop and Oski!

Cheers

Anu

Srini, PSL-VHDL ...

teamspecman — Thu, 15 Dec 2011 23:56:52 GMT

Srini,

PSL-VHDL is on Specman plan, we hope it will be released in 2012. Stay tuned ...

Team Specman

I am the owner of da ...

Anonymous — Tue, 13 Dec 2011 03:13:12 GMT

I am the owner of dalTools LLC. Please take a minute to look at our website. These are tools that work with Cadence Allegro to improve the PCB design process dramatically. I would very much like to join the connections program. If you think this company is a candidate for the connections program please contact me through the web site. Thank you, Dal Locke

This is great featur ...

Anonymous — Thu, 08 Dec 2011 16:49:29 GMT

This is great feature. Why is it only for PSL-Verilog/SVA and not for PSL-VHDL? We are now starting a customer project with VHDL & E and PSL. Would be great to have this now!

Thanks

Srini

www.cvcblr.com

Scheng, Thanks fo ...

Anonymous — Wed, 30 Nov 2011 18:39:04 GMT

Scheng,

Thanks for noticing the problem with the file. We had a problem uploading that left the zip corrupt. We tried it from both Chrome and IE and it works.

=genIES

Hi, would you please ...

Anonymous — Wed, 30 Nov 2011 06:56:06 GMT

Hi, would you please check your download link and file again, because I am getting errors while trying to extract the ovm_reg_2.7.1.tar.gz. It seems the archive is damaged. Thanks.

Yes, this approach i ...

TeamVerify — Thu, 03 Nov 2011 15:05:38 GMT

Yes, this approach is creating the basic infrastructure required to stimulate asynchronous input clocks. The next step would be to inject meta-stability effects like variable delays on clock domain crossing paths. This is also possible in IEV using cutpoints and interactive Tcl constraints for example. I'll consider describing this in a subsequent blog

This approach seems ...

Anonymous — Thu, 03 Nov 2011 13:41:04 GMT

This approach seems not to change the order of the arrival of

signals which cross clock domains in parallel.

e.g.

In good case, the receving clock domain catches the changes

at the same clock edge. In the bad case, at least one event

comes a clock period later.

Make sure you have a ...

TeamVerify — Mon, 31 Oct 2011 15:41:12 GMT

Make sure you have a Cadence Support account -- it's free included for all customers with paid maintainence. Go to support.cadence.com, and click on "Register Now" to sign-up yourself.

Congratulations to t ...

Anonymous — Sun, 30 Oct 2011 02:37:27 GMT

Congratulations to the Formal team on the success of IEV and IFV and for shining through CDVLive with all the papers and awards. The spate of papers on the topic of Formal's integration with Simulation proves that it is the most interesting and challenging topic on Functional Veriification, still innovating and exciting interest in the User community.

Lokesh, I agree with your phrase".....blessed with an embarrassment of riches!"

--Anu

Hi, How do I view t ...

andare — Fri, 21 Oct 2011 21:50:34 GMT

Hi,

How do I view these videos?

Thanks

Ananda

If we compare the ac ...

JoergM — Thu, 20 Oct 2011 15:04:19 GMT

If we compare the actual state space created by a environment with fully asynchronous clocks and clocks with a defined frequency range (like one edge within [0:20cranks] then we find that the first approach adds 1 state bit, while the second adds a 5bit counter for every clock (counting up to 20). So we can expect that the asynchronous environment is less complex.

We recommend to not use such auxiliary counters (especially in the clock tree) until we absolutely require it.

I think this approac ...

_temp_05ef986e-c806-43b5-856b-09142d639f72 — Tue, 18 Oct 2011 12:38:08 GMT

I think this approach may not really help in large designs because if clocks are also considered as free inputs, the state space becomes really huge and many properties will explore (depending upon complexity of design). A better approach would be to ensure a rising edge on each clock atleast once between say [0:20cycles]

If you go to http:// ...

tomacadence — Mon, 17 Oct 2011 20:23:46 GMT

If you go to www.cadence.com/.../event.aspx you can now view the archived version of this Webinar, Enjoy!

Tom A.

All of our functiona ...

tomacadence — Fri, 14 Oct 2011 19:38:37 GMT

All of our functional verification Webinars are archived; this one should be available within a week or two. I will post a note here when it is available on www.cadence.com/.../archive.aspx

Tom A.

I would like to watc ...

_temp_54c7a03a-c7d9-464f-b398-207c53c0521b — Fri, 14 Oct 2011 01:30:30 GMT

I would like to watch this webinar since I missed it, how can I do that

The support for PSL ...

Michal Nevo — Mon, 03 Oct 2011 11:57:08 GMT

The support for PSL (Verilog only) is added in 10.2s70

Thanks,

Michal

Anu, Thanks for t ...

tomacadence — Thu, 29 Sep 2011 23:27:08 GMT

Anu,

Thanks for the kind words. It is ironic that a medium capable of providing worldwide instant updates has so much content that is out of date.

Tom A.

Hello,great stuf ...

Anonymous — Thu, 29 Sep 2011 08:37:08 GMT

Hello,

great stuff! :)

I'd really like to use it, but we are having PSL assertions here ...

Now, the HDL_ASSERT_LANG enumeration type (according to the documentation i have) has the following values:

OVL_V1, OVL_V2, OVL and SVA

No mention of PSL ...

So my question is: Can this be used with PSL assertions?

Florian

This is tremendous. ...

Anonymous — Wed, 28 Sep 2011 20:39:35 GMT

This is tremendous.

Very concise and much better than the slides I've seen on the topic in the past. I guess the big question is "when should I use this?" For what use cases is this good for?

Thanks,

- Silas.

Tom,This is an i ...

AB777 — Wed, 28 Sep 2011 03:55:44 GMT

Tom,

This is an interesting thread that is why you have maximum reads and comments . True experiences in the "paperless word of computers" and how sometimes they bother you!

I recently had an experience then I was booking ticket for a Theme park online. When I searched Google I got to see some offers on particular credit cards. So I was all set to do a bulk booking since I had that particular card. Only to realize later while filling forms at such an offer was valid in 2010 and "conditions apply" and "FCFS basis" :(

--Anu

Gaurav,I agree 1 ...

tomacadence — Tue, 27 Sep 2011 19:34:55 GMT

Gaurav,

I agree 100% that multi-language UVM is interesting and useful. As you know, Cadence has contributed e and SystemC UVM libraries to UVM World, and we are encouraging Accellera to extend the standard to include full multi-language support.

Tom A.

IMO, multi-language ...

Anonymous — Mon, 26 Sep 2011 11:13:51 GMT

IMO, multi-language support in UVM probably would be more interesting & useful. I believe it is the language that makes UVM look tedious. Maybe if it was tried on 'e' first and then extended to SV, the blog post title would have eliminated "UVM" probably.

whatisverification.blogspot.com

Anantharaj,NextO ...

Anonymous — Sat, 24 Sep 2011 15:41:01 GMT

Anantharaj,

If the RTL is buggy, but there is no checker failure, there are two possible reasons: 1. insufficient stimulus, i.e. the test vectors did not exercise the bug. 2. insufficient checkers, i.e. the bug is exercised, but not caught by a checker.

For case 1, the stimulus is still good. NextOp can generate high quality assertions and cover properties. In addition, the coverage properties may point out coverage holes that guide the user to add test vectors.

For case 2, a. NextOp assertions from neighbor blocks may trigger and expose the bug (sometimes an assertion trigger can point to a RTL bug in its neighbor modules) or b, NextOp may generates a property that "does not make sense" to designer, but in reviewing the properties, the bug is exposed.

We've seen many real life examples of case 1, case 2a and case 2b.

Hope this helps.

Yuan Lu, NextOp

Anantharaj, Than ...

tomacadence — Sat, 24 Sep 2011 00:43:24 GMT

Anantharaj,

Thanks for your excellent question. NextOp does not claim that its assertion synthesis can generate all assertions or catch all bugs. It is certainly possible that its assertions could miss a bug.

However, the presence or absence of checkers in the simulation testbench does not matter. NextOp’s tool reads only the design and the simulation results, so as long as the simulation does a good job of exercising the design then high-quality assertions will be generated. In particular, it’s quite likely that NextOp will generate some assertions that do not have any corresponding checkers in the testbench.

Tom A.

Hi Tom,Thank you ...

Anonymous — Wed, 21 Sep 2011 10:16:04 GMT

Hi Tom,

Thank you for the blogs on Functional verification.

I have a basic question on generation of SVA & Coverages using a tool.

My concern is that this assertion synthesis may leave out a hidden bug in the design, by just reading the RTL & simulation database -> to generate the SVA.

What if there is a bug in the RTL & there were NO checkers associated with in the Constrained random environment?

This results in SVA generated by the tool, using a faulty RTL & a missing checker CRV environment simulations.

Please calrify on the same.

Hello QiangGood ...

teamspecman — Tue, 20 Sep 2011 18:22:37 GMT

Hello Qiang

Good to hear that you are learning e and would like to get the Specman/e manuals translated in Chinese. I will forward your request to the local Cadence China team and they can support you. Feel free to send me your contact info and I can ensure that the local team can contact you. My email address is karnane@cadence.com

Regards,

Kishore Karnane

Tom,I did see th ...

tomacadence — Mon, 19 Sep 2011 23:37:51 GMT

Tom,

I did see that blog post; kudos to Mentor for commissioning the survey and to Harry for offering some very interesting analysis. Specific to Specman/e, your survey reports a slight dip in usage from 2007 to 2010. I just ran the numbers from our internal sales system, and have the hard data that the number of Specman licenses in active use by our customers grew significantly over this same period. No matter how carefully a survey is done, it is after all only a sample.

Your survey also suggests a drop-off in Specman/e usage over the next 12 months. I've commissioned and analyzed surveys too, and one very common result is that respondents over-estimate how quickly their environment will change. I'm sure that some Specman/e users feel that they will be forced to switch to SystemVerilog but I predict that far fewer will actually do so. Further, we've seen several projects try SystemVerilog and then switch back to e because they lost 30-40% efficiency:

* www.cadence.com/.../user-view-where-e-outshines-systemverilog-for-functional-verification.aspx

* www.cadence.com/.../user-view-is-e-or-systemverilog-best-for-constrained-random-verification.aspx

On the other hand, I do believe that usage of eRM and URM is declining. UVM is the standard, and with Cadence's contributed e and SystemC extensions paving the way it's natural for users of all older methodologies to switch to multi-language UVM regardless of their language or mix of languages. UVM is the way forward; surely we agree on that!

Tom A.

Looks like "rumors o ...

Anonymous — Mon, 19 Sep 2011 15:02:34 GMT

Looks like "rumors of SystemVerilog's death" aren't the only thing being greatly exaggerated. If you look at blogs.mentor.com/.../part-8-the-2010-wilson-research-group-functional-verification-study you'll see the results of a blind study by Wilson Research Group showing that usage of 'e' is actually shrinking (Figure 4), as is usage of eRM (Figure 5).

Hi, I come from chin ...

Anonymous — Mon, 19 Sep 2011 08:55:33 GMT

Hi, I come from china, I am a junior in e learning, so need look up the manual frequently,but the English version seem too difficult for me to understand. I believe there are many people has the same problem as me. So I write this letter to ask you make a Chinese version. Think you, I am looking forward you replay!

Horace, Many engi ...

tomacadence — Fri, 16 Sep 2011 21:58:08 GMT

Horace,

Many engineers consider e a more elegant and focused language than SystemVerilog for verification. I agree that public statements of support from other vendors would be beneficial to e's large and growing user community. We can't make that happen ourselves but perhaps the users can if they keep pushing!

Tom A.

We don't need a new ...

Anonymous — Fri, 16 Sep 2011 05:29:42 GMT

We don't need a new verification language, there is Specman e

We only need need the other two EDA companies admit they also support IEEE1647.

Gaurav, thanks for s ...

tomacadence — Thu, 15 Sep 2011 18:42:09 GMT

Gaurav, thanks for sending the links and reminding me about your posts. I read them when they came out and thought that they were really good. I recommend them to my readers.

A quick summary on t ...

Anonymous — Thu, 15 Sep 2011 08:02:29 GMT

A quick summary on the need for GLS -

whatisverification.blogspot.com/.../gate-level-simulations-necessary-evil.html

whatisverification.blogspot.com/.../gate-level-simulations-necessary-evil_29.html

whatisverification.blogspot.com/.../gate-level-simulations-necessary-evil.html

Good questions Sande ...

Jack Erickson — Tue, 13 Sep 2011 19:30:02 GMT

Good questions Sandeep. High-level synthesis tools, such as C-to-Silicon Compiler raise the abstraction of your input code, so you don't need to worry about where to insert flops. C-to-Silicon will then analyze all paths to maximize the available time, and squeeze as much logic as possible into each path. C-to-Silicon does this analysis by using the Cadence RTL Compiler logic synthesis tool under the hood, so it can accurately time each path, and ensure that the generated RTL will predictably close timing.

Pipelining is another big advantage in using C-to-Silicon since you don't need to hardcode any of the pipeline structures in the input SystemC; just focus on the algorithm and let C-to-Silicon implement it in a varying number of pipeline stages to compare overall area, latency and throughput. Then if you want to increase the clock frequency, simply re-run the pipeline command to achieve a different number of stages to meet timing.

Regarding DDR memories, yes C-to-Silicon supports any memories that memories compilers generate, and does not care about internal memory implementations.

A college friend wit ...

tomacadence — Mon, 12 Sep 2011 21:32:51 GMT

A college friend with whom I attended a bunch of Ramones concerts back in the day reminded me that they adapted "Doreen is never Boring" into the song "Touring" ten years later. For those interested in the original version by The Mystics, I found it on CD at http://bit.ly/r53XGB and MP3 at http://amzn.to/qhtsc0. Enjoy!

Hi, I would like ...

Anonymous — Tue, 30 Aug 2011 09:56:06 GMT

Hi,

I would like to know more about how the untimed SystemC model will be converted to Netlist ? More specifically, where would the HLS tool put flops so that the timing is met ? How about advanced timing features like pipelining ? How about supporting DDR ?

regards

Sandeep

Is it possible to ru ...

Anonymous — Sat, 27 Aug 2011 19:20:02 GMT

Is it possible to run the simulations with other simulators using irun ??

Hello Tzachi, Tha ...

Anonymous — Wed, 24 Aug 2011 01:44:17 GMT

Hello Tzachi,

Thanks for trying out the Intelligen example. Based upon your comment, it seems like you may be using an older version of Specman/e. We have updated the Incisive 10.2 release with many enhancements around nested “keep for each” functionality. I would encourage you to upgrade to the latest Incisive 10.2 release and try out this example. I am quite sure that will fix the problem. You can download the latest 10.2 release from http://download.cadence.com site

Feel free to contact me if you have already tested the example with the Incisive 10.2 and are still experiencing the same issue. You can contact me via email: lagoon@cadence.com

Regards,

Vitaly Lagoon

Currently there is n ...

Anonymous — Tue, 23 Aug 2011 18:45:19 GMT

Currently there is not a stand-alone student version of Specman or IES-XL. However, if your school is part of our University Program you can get access to our software via your school's systems. If your school is not currently in the program, by all means we welcome you/your school to apply. Here is the web page with all the details: www.cadence.com/.../default.aspx

is cadence student v ...

Anonymous — Tue, 23 Aug 2011 11:25:00 GMT

is cadence student version available as a free software for the engineering students?

Here's what I get: ...

Tzachi Noy — Tue, 23 Aug 2011 11:09:11 GMT

Here's what I get:

(you can see that the solution is incorrect)

Specman queens> test -seed=1

Doing setup ...

Generating the test with IntelliGen using seed 1...

Starting the test ...

Running the test ...

Q . . . . . . . . . . . . . . . . . . .

. . . . . . . . . Q . . . . . . . . . .

. . . . . . . . . . Q . . . . . . . . .

. . . . . . . . . . . . . . . . . . Q .

. . . . . Q . . . . . . . . . . . . . .

. . . . . . . . . . . . . Q . . . . . .

. . . . . . . . . . . . . . . . Q . . .

. . . Q . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . Q . . . . .

. . . . . . . . . . . . . . . . . . . Q

Q . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . Q . .

. Q . . . . . . . . . . . . . . . . . .

. . . . . . . . . Q . . . . . . . . . .

. . . . . . . . . . . . Q . . . . . . .

. . . . . . . . . . . . . Q . . . . . .

. . . . . . . . . . Q . . . . . . . . .

. . . Q . . . . . . . . . . . . . . . .

No actual running requested.

Checking the test ...

Checking is complete - 0 DUT errors, 0 DUT warnings.

Indeed, this was rus ...

Anonymous — Tue, 23 Aug 2011 00:29:12 GMT

Indeed, this was rush hour in the heartland of Minnesota. What was the give-away, the miles of corn or the miles of soy beans? ;-) We were going to capture you and drag you into one of the meetings, er, I mean, we were going to stop by and say 'hello' but you were on vacation during this week.

Joe, looks like heav ...

jasona — Wed, 17 Aug 2011 13:17:20 GMT

Joe, looks like heavy traffic in the picture, any chance one of the states was Minnesota?

Thanks for the examp ...

tomacadence — Tue, 16 Aug 2011 18:45:26 GMT

Thanks for the example and the feedback, Jim!

Tom A.