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Functional Verification Blog

Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture) package features the ability to transfer objects from one verification framework to another via multi-language TLM ports. Check out Appendix A if you are a first-time...  Read More »
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Troubleshooting Incisive Errors/Warnings—nchelp/ncbrowse and Cadence Online Support

I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor who I could ask all my queries. But most of the times, I was on my own...  Read More »
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My First Internet of Things Device: Moving from a Manual to an Automated Process—Debug Analyzer vs. Simple Logging

Adopting the Internet of Things for home automation. Drawing a parallel to verification debug with Icisive Debug Analyzer...  Read More »
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Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components

What happens when you have two verification components (for example one implemented in e and the other in System Verilog) and one of the frameworks drops its last TEST_DONE objection?...  Read More »
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Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Display

The Retina display in the Apple MacBook Pro has much more value than I originally expected. As similar observation is being made about the Incisive debug Analyzer....  Read More »
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Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More

The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than verification. Today, with the increase in number of performance...  Read More »
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Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support, 2Q 2014

Cadence Online Support, http://support.cadence.com , provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to interact with Cadence Customer Support. In the June release...  Read More »
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Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it...  Read More »
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Updates from the UVM Multi-Language (ML) Front

An updated version of the UMV-ML Open Architecture library is now available on the Accellera uploads page (you need to login in order to download any of the contributions). The main updates of version 1.4 are: UVM-SV library upgrade: This release includes...  Read More »
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sync and wait Actions vs. Temporal Struct and Unit Members

Using sync on a temporal expression (TE), does not guarantee that the execution will continue whenever the TE seems to succeed. In this example, the sync action will miss every second change of my_event: tcm0()@any is { wait; while TRUE { sync change...  Read More »
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