Functional Verification

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

2012-01-30T14:00:00Z

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach to verification performance you can use immediately at all levels from core simulation to advanced technologies and methodologies.

For certain, the most common use of simulation is RTL and gate-level simulation. During 25 years since the start of the RTL era, Moore’s law has held true as designs have doubled every 24 months. While the design work is still all done in IEEE 1076 and 1364 (+1800 since 2005 and now some 1666), verification productivity, predictability, and quality is now derived from an ever-increasing suite of standard languages and methodologies. The result is that the typical simulation run today employs a wide range of features beyond RTL and gate.

That history lesson is probably common knowledge, but how to deal with the performance requirements of advanced node SoCs isn’t. Because of all the complexity, the simulator has to be measured in multiple ways to build-in the best performance. That will give us a fast simulator, but if we run that simulator using the golden scripts we created years ago the effect on this fast engine is akin to strapping model-T tires on an F1 car. After we’ve got all the elements of our simulation balanced for performance, it’s time to dig deeper into the code we’re running on the engine. Sure, that code is running accurately, but is it running efficiently? The simulator is just going to execute the code we provide, so we need to profile our code and find algorithms that get the same task done but do it faster. We introduce this last concept in the white paper, but that’s a teaser for a DVCon 2012 SystemVerilog performance paper. Stepping back from profiling, keep watching this blog stream for application notes that will help you implement the ideas in this core simulation section of the white paper.

Now that your simulations are running fast, where do you go to get even more performance? The “Advanced Node SoC Verification Requirements” section of the white paper introduces several technologies and methodologies that, with varying degrees of investment, can provide substantial improvements in performance and productivity. If you are at or below 40nm, or planning to go there, pay careful attention to this section and the Advanced Verification Topics book to understand the options you have for further performance improvements.

When Cadence pioneered commercial simulation with Verilog-XL 25 years ago, life was simple. Chips were designed in schematics, and RTL and gate simulation was all we needed. Simulation has come a long way from those days and is even more relevant in today’s complex chips. This white paper will help you understand how the Incisive Enterprise Simulator has adapted to today’s advanced node SoCs and how it will continue to scale for tomorrow.

=Adam Sherer

Video Killed The Reference Manual Star

2012-01-26T14:00:00Z

[Preface: recall the melody of the Buggles' 1979 hit "Video Killed the Radio Star" as you read the following]

Q: What is your favorite pastime?

A: Reading reference manuals!

No? Really?

OK -- with all due respect to our Tech Pubs team, virtually no one wants to sit down and read reference manuals if they can help it. And in a perfect world, it should not be required in the first place. Alas, our world is not perfect, but that should not preclude us from striving toward Nirvana.

And thus, I assert that for many, a good picture says more than a thousand words. It is a cliché, but it is true. However, even the most complete infographic might not always be sufficient to convey a concept or feature - particularly if you do not have someone providing verbal context to the picture. Thus, moving pictures -- videos -- can convey certain concepts more effectively and will have a longer lasting (memorization) effect than a reference manual.

Hence, Team Verify has produced the following series of short, focused videos on various aspects of formal and ABV techniques. All of them are short (around 5 minutes) and focused -- we've posted the "Introduction to Assertion-Driven Simulation" to give you an exact idea of what you can expect. The rest of the videos require a Support login ID only.

Assertion Driven Simulation
Introduction to Assertion-Driven Simulation (YouTube-based sample)
Soft Constraints in Assertion-Driven Simulation
Dead Ends in Assertion-Driven Simulation
Seeds in Assertion-Driven Simulation

Tool Basics
Introduction to Interactive Properties
Local Property Distribution
Property Distribution using LSF
Engine Distribution
Introduction to Cutpoints
Introduction to Initialization
Localization Abstraction & Halo

Concepts
Introduction to Cranks

Methodology and Flows
Introduction to Formal Scoreboarding
Introduction to the Coverage Unreachability flow

Enjoy!

Axel Scherer
Solution Architect
For Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

UVM: "Everything that Can be Invented Has Been Invented" Not True!

2012-01-26T14:00:00Z

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology (UVM) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that build on the UVM to serve the requirements of advanced node SoCs.

The Accellera Systems Initiative UVM is gaining great momentum in the industry. From the Cadence perspective, our customers starting new SystemVerilog projects are doing so with UVM, and those starting new e projects are doing so with our e-based equivalent. Those customers are enjoying the reuse that is built into the UVM and the Cadence differentiators that work with the UVM like verification IP and debug. But the wise verification lead faced with low-power, massive designs, multi-language IP, and more challenges that seem to be prevalent at 40nm and below is asking -- what's next?

The Advanced Verification Topics book describes what's next. The five chapters, expertly described by Richard Goering in his blog, introduce methodologies that will improve productivity, predictability, and quality building on the UVM methodology base. Verification engineers reading this book will gain an appreciation for the work that needs to be done to implement these methodologies and the potential gains they represent.

In stark contrast to Mr. Duell's quote, Cadence has only just begun. Watch us in 2012 as we introduce several other topics and expand the languages used in our examples. We have a bigger boast for verification -- everything that can be invented WILL be invented and quite likely it will be from the engineers at Cadence.

=Adam Sherer, MS EE, BS EE, BA CS

** Note: Dennis Crouch's research suggests the quote actually comes from a 1899 humor magazine that described a fictitious exchange between a genius and a young lad at the patent office.

Event Report: Club Formal UK – Cache Coherency, UVM for ABV, and Brainstorming with R&D

2012-01-24T19:56:00Z

Right before the December holidays it was my privilege to host the first "Club Formal" here in the U.K. My colleagues and I welcomed over 20 power users from 8 different companies, providing an exciting diversity of ideas and applications. We also took the opportunity to sneak preview some new technologies, share our product roadmap, and discuss new requirements from the attendees to better align our R&D development with their needs.

(If the image gallery doesn't open, click here.)

Here are some specific highlights of the event:

Customer Presentation: Finding A Cache Coherency bug with formal
In a very motivating talk, engineer David Lewsey shared how he was able unearth a nasty cache controller bug -- something engineers had not been able to detect with simulation -- via a clever combination of optimizing the design and applying abstraction methodologies. Specifically, putting some parameters in the code can really reduce the size of the design that the tool "sees." Plus, you can avoid modifying the RTL with concurrent, judicious applications of cut points, forces, and init commands in TCL scripts. In roughly the same amount of time it would have taken just setup a block level test bench, they were able to uncover the root cause of a complex bug that had eluded detection for some time.

Presentation: UVM with ABV
In this talk and supporting demo, Kong Woei Susanto showed how the basic principles of the popular Universal Verification Methodology ("UVM") can be readily extended to the formal and assertion-based verification (ABV) space. In the context of an easy to understand router example, Kong showed how simple reuse techniques/templates, and coverage-driven driven verification methodologies so common in the dynamic simulation world map directly to ABV and how the strengths of formal techniques can be used to compliment weaknesses in a pure simulation flow.

Keynote speech on "Verifying Memory Coherency"
Continuing on the cache coherency theme, it was a real treat to introduce R&D Fellow Bob Kurshan, a true pioneer in the field of formal analysis (remember the ground breaking "Formal Check" tool?), to present a deep dive on the challenges and pitfalls of cache and memory coherency verification.

Panel Discussion
Yours truly was honored to lead the panel discussion with Solutions Architect Joerg Muller, and our AE speaker Kong Woei Susanto to brainstorm with the audience on a wide variety of topics. Allow me to publicly thank the attendees again for being so generous with their thoughts and recommendations, which was to the benefit of all!

Training, Roadmaps and new Product Previews
Allow me to again thank the attendees for their warm reception of our product roadmap, and being generous with comments about where you'd like to see more attention. This feedback is invaluable to R&D, and as you saw we were all taking careful notes. In addition, the attention paid to the coverage unreachability and formal scoreboarding reviews made it clear these were areas of high interest for everyone.

Lunch, Snacks, and Happy hour!
Last but not least, the intermissions and social segments of the day were of high value as well. Whether it was the casual lunchtime discussions, or informal Q&A at the pub, truly these venues -- comfortable, community settings where users get to swap stories with other users to brainstorm solutions and share tips and tricks -- were some of the best parts of the day.

Bottom-line: an engaging, informative time was had by all, and I believe I speak for everyone in looking forward to the next event later in 2012!

Until the next Club Formal, happy verifying!

Vincent Reynolds
Application Engineering Leader
Bracknell, UK
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

P.S. Team Verify is working on the 2012 event calendar now. Hence, this the perfect time to let us know If you would like to see a Club Formal in your area! Simply jump to the Team Verify home page and "send Team Verify a private message".

P.S.S. In case you are unable to attend a Club Formal near you, be sure to check out our archive of free, technical webinars:
http://www.cadence.com/Community/blogs/fv/archive/2011/12/27/free-formal-amp-abv-webinar-recordings-from-2011-online-now.aspx?postID=1306428

2012 CES: Top 3 Trends Impacting EDA This Year

2012-01-17T22:00:00Z

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't personally attend CES this year, I had two trusted agents (specifically, Unified Communications (UC) expert David Danto of Dimension Data, and Joseph Hupcey Jr., video & communications systems architect and father of yours truly) on the ground to field check the myriad of reports streaming in from legacy and new media. Thus, allow me to highlight the following three trends from CES 2012 that I suggest will have a big impact on EDA this year.

1. TV's rapid evolution: ahead of the equally dramatic and lucrative transition from feature phones to smart phones, virtually all TVs shown at CES were "smart." Specifically, as the EDA360 vision paper foretold, it's not enough for TVs to support passive visual entertainment. Instead, the TV of today must support a library of interactive apps, coupled with some sort of digital video recording (DVR) solution to be viable in all but the most niche markets. That said, EE's and physicists alike should take comfort that raw hardware can still deliver its own differentiating punch: my agents reported several very good, "no glasses" 3-dimsenional displays, where the best of show was LG's prototype OLED 3D display. Quoting David Danto's eyewitness account:

"Hands down - no contest, my pick hit of the show is LG's new 55 inch OLED 3D display. ... I've been evaluating displays for most of my 30 year career and I've never seen anything that looked as good as this. First of all, it uses LGs passive glasses technology. No electronic shutters, no charging, no feeling like a reject from Tron. Then, the actual images sacrifice nothing to achieve the 3D effect - bright, vivid, lifelike colors, deep blacks, true whites. Then, to top it all off, it is so thin that from the side the thing is practically invisible."

(Note: from my experience, I agree that no picture or contemporary video can do a well sourced OLED justice -- to give you some idea of the bold visual character of an OLED's imagery, try to imagine a living magazine animated with rich, saturated colors like you get from the best dye sub printers.)

So what's the bottom-line for EDA for all this TV innovation? In a word, growth. How? This new generation of TVs deliver a visibly different experience than the best "dumb" TVs of even a few years ago -- they will inspire new sales / upgrades. Granted, you might be able to extend the "useful" life of a good-yet-dumb screen via web enabled boxes like TiVo DVRs and BlueRay players (like I'm doing with my 4 year old Sony Bravia LCD). But either way -- via new TVs or new set top boxes -- many more SoC's and peripheral IC's will be shipped.

2. ARM vs. Intel competition: While ARM is justifiably proud of the plethora of sockets they supported across the show floor, Intel fired a substantial broadside with the announcement they would be sourcing Atom architecture processors for Motorola Mobility (read, "soon to be Google", and all the Android market reach that implies) and Lenovo (read, "China and rest-of-world!"). In a provocative article "How Intel's Medfield Will Dismantle ARM", author Sebastian Anthony asserts that these announcements are only the opening salvo, and that Intel will be able to leverage their research and manufacturing strength to "physically" outpace competitors stuck on bigger nodes. Indeed, while ARM has a lot of momentum to say the least, Intel's tantalizing hints last December that they have 14 nm devices working in the lab gives credence to Anthony's aggressive theories. As for myself, I'll make the oh-so-daring prediction that whoever can deliver the best MIPS/watt by a >= 50% margin will be the ultimate victor.

3. The future of CES itself, and lessons for DAC: despite record breaking attendance, my agents confirm that there was palpable undercurrent of dissent -- fed by Microsoft's announcement that this was their last CES -- that the value of CES has diminished and/or is not aligned with the needs of the industry. This expression of frustration about misalignment between show management and attendees triggered a personal flashback to the very last COMDEX (despite it being a very productive show for my company, where we sold hundreds of eyemodules in the temporary Handspring store between the exhibit halls).

Suffice to say there has been a lot of punditry about the future of the Design Automation Conference (DAC) over the past several years. Aside from concerns about maintaining a forum for startups to introduce themselves, what seems to be missing are customers coming forward en-masse demanding that the show must go on. To wit, in past years major semiconductor and systems houses would send dozens of front line engineering managers and developers, CAD staffers, and R&D executives. Now you are lucky to see those same companies send a lone VP accompanied by 1-2 CAD managers. And from the vendors' point of view, is it all worth it, in terms of marcom dollars ROI, or from the more abstract "branding" value? Time will tell ...

Joe Hupcey III

On Twitter: http://twitter.com/jhupcey

P.S. Speaking of trade shows, in the verification space the annual DVCon's clear focus on functional verification technology and methodology has made it a growing, high value technical and trade forum. Hence, my colleagues and fellow bloggers will be there in force! In particular I welcome you to join me at the tutorial I'm hosting, entitled "Using "Apps" to Take Formal Analysis Mainstream", on Thursday March 1 from 8:30am-Noon (includes coffee & lunch) Register today!

Video: Bob Kurshan, Cadence Fellow and Incisive Formal R&D Leader, talks about Formal Engine Tech

2012-01-05T21:00:00Z

Continuing the series of introducing you to the people that create the tools you use every day, in this video I ask Bob Kurshan, Cadence Fellow and R&D leader of the Incisive Formal Verifier ("IFV") "Engines Team," about the challenges and/or tradeoffs in creating a formal engine, how to avoid gotchas in tricky problems like cache coherency verification, and how formal technology might evolve over the next 5 years.

If the embedded video doesn't play, click here.

Please feel free to ask Bob questions via the comments below; or jump to the Team Verify home page to "send Team Verify a private message" for forwarding to him offline.

Joe Hupcey III
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Reference links to prior R&D interviews:
Distinguished Engineer Alok Jain

Incisive Formal R&D team leader Deepak Pant

Incisive Enterprise Verifier R&D Architect Vinaya Singh

Incisive Formal Verifier R&D leader Pradeep Goyal

Free Formal and ABV Webinar Recordings from 2011 Online Now!

2011-12-27T14:00:00Z

In case you missed any of the 5 free webinars Team Verify presented in 2011, you're in luck: all of them have been recorded and posted for you to review at your leisure. Take your pick from the following - or pop a bucket of popcorn and a family sized bag of chips and watch them all at once!

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How to Completely Eliminate SoC Connectivity Bugs - Really!

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=516

Bugs from incorrect connectivity -- whether they're misconnected IP blocks inside an SoC or erroneous muxing of pad rings -- can kill a chip just easily as more sophisticated functional bugs. With internal connection points surpassing hundreds of thousands of nodes, the traditional approach of assigning detail-oriented summer interns to spot-check connectivity with dynamic simulations is rapidly losing effectiveness. How do you ensure that two versions of your design are equivalent (e.g., the design before power techniques and after)?

In this technical webinar, we'll show you how to apply formal verification technology to exhaustively prove with 100% mathematical certainty that all of your SoC's internal and external pad ring connections are completely correct. An included demonstration (recorded live) reinforces the concepts presented.

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Verification 1-2-3 with Assertion-Driven Simulation

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=518

This is it: a simple, straightforward methodology that increases bug detection and produces much cleaner RTL. Totally revolutionary "assertion-driven simulation" leverages easy constraint and assertion properties to simulate, visualize, and debug your design -- plus drive coverage collection.

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Automate Assertion Generation for Simulation, Formal and Emulation Flows

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=557

Assertion-based verification (ABV) helps design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that define the intended behavior of signals in the design.

The emergence of "assertion synthesis" allows for true proliferation of ABV by automating the often painful manual process of creating meaningful white-box assertions and functional coverage properties with sufficient capacity to handle complex SoC designs. Without writing any additional code, stimulus generation and additional tests will find additional bugs and improve functional coverage, integrating into your metric-driven verification (MDV) flow.

In this webinar, Cadence and NextOp Software show how assertion synthesis enables a progressive, targeted verification process, allowing design and verification teams to more easily uncover corner-case bugs, expose functional coverage holes, and increase verification observability. The included demonstration (recorded live) reinforces the concepts presented during the session.

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Quickly Find Data Transport Bugs with Formal Scoreboarding

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=560

"Scoreboards" have been used in advanced simulation testbench environments for years. In this webinar we will show how this same concept can be implemented with formal verification tools. Consequently, you will see how to benefit from powerful formal analysis algorithms to automatically test data integrity and root out the spectrum of simple problems to extreme corner cases.

The formal scoreboarding methodology is flexible and extendable such that it can be applied to various data transport blocks including bridges, switches, routers, matrices, memory controllers, DMA controllers, and buffers. Its value to the user is a significant reduction in simulation runtime and the ability to find bugs faster with less effort. This is an exciting topic for anyone in the functional verification space.

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Simplifying Code Coverage Analysis: Automatically Separating the Wheat from the Chaff

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=562

Code coverage is a popular methodology let alone a signoff criterion for many companies. Unfortunately, code coverage can produce an enormous number of objects, where analysis of even a small number of coverage holes can be very tedious and time consuming. Of course, completely ignoring those holes can introduce risk that might not be acceptable.

In this webinar, we show how new automation and a revolutionary "case-splitting" methodology can help you separate the wheat from the chaff -- the "reachable" versus the "unreachable" code coverage holes. While formal analysis engines (and the mathematical certainty they offer) are used under the hood, perhaps the best part of the new case-splitting approach is that the flow does not require any understanding of formal analysis and is accessible to anyone familiar with simulation. This is an exciting topic for anyone in the functional verification space. The included demonstration (recorded live) reinforces the concepts presented in the lecture portion of the presentation.

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Happy learning and Happy New Year!

Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Some Final Real-World Assertions for the Holidays

2011-12-20T16:05:00Z

My last "real-world assertions" blog post seems to have tickled a bunch of people with my story about the racy narration at the historic Red Fort in Delhi. I've heard from several folks who have also seen the show and had a similar reaction. Just out of curiosity, I did a Web search and found a half-dozen or so other blogs and travelogues with comments similar to mine. Concluding my series, and in the spirit of the holiday season, here are a few final amusing incidents related to shopping that would also have benefitted from assertions.

The first occurred as I was browsing the DVD shelves in Space Cat Comics, a San Jose institution that has a big selection of used music and movies in addition to comics and collectables of many kinds. This particular portion of their selection contained bargain releases, primarily movies and TV shows now in the public domain. My attention was drawn to a very inexpensive four-movie collection entitled Hollywood Classics: Alfred Hitchcock. I'm a big fan of Hitchcock's work so I pulled the DVD off the shelf to take a look.

I was amused to see that the four movies included were The 39 Steps, The Man Who Knew Too Much, Secret Agent, and Sabotage. These are all good titles; in fact The 39 Steps is widely regarded as the first truly great Hitchcock film. However, all four were made in the U.K. in the 1930s, well before producer Davis O. Selznick lured Hitchcock to Hollywood to make Rebecca and start the American phase of his career. These are not "Hollywood classics" at all, and the kicker is that this DVD is released by the "Genius Entertainment" brand.

My second example comes from an email message sent by BookBuyers in Mountain View, the largest used bookstore in Silicon Valley. They also have lots of used movies, music, video games, computer software, magazine, comics, and more. I can easily lose track of time and spend hours browsing there. The email message included a discount coupon with the following statement:

Thanks for making Small Business Saturday such a success last week. Many people asked for more time to use their coupons, so... buy one, get one half off again this Friday, Saturday and Sunday, December 3, 4 and 5.

Of course, the first weekend of December 2011 was actually the 2nd, 3rd, and 4th. The bottom of the message said "Valid 12/2/2011 - 12/4/2011" so it wasn't even self-consistent. We all make typographical errors, and in past posts I have not elevated garden-variety typos to the status of missing assertions. So why tease a bookstore that I really like? This particular case made me chuckle because BookBuyers is especially well known for having a big selection of calendars at great prices. They seemed like the last folks I would expect to mix up dates.

My final example also involves a typo, but one of the more dramatic I've seen in a while. A recent EE Times article presented a top 10 list of innovative USB devices that might make nice holiday gifts. One of the more unusual entries was the "Infinite USB Memory (IUM)" stick from Infinitec. This USB stick has no actual memory inside; instead it sends the data to a laptop via a wireless link. I'll admit I had to scratch my head a bit over that concept. If you need to transfer more data than today's high-capacity USB drives hold, it would take a long time to do so wirelessly.

But what really caught my eye was what appears to be a screen shot in the article. At the top appear the words "Infinte Portal" rather than "Infinite Portal" as one would expect. I checked the company's site, and the same image appears there. Sure, I've had my share of embarrassing typos, including in this blog, but the "Infinte" type appears to have been coded into the Infinitec laptap GUI and propagated in many forms. Presumably it was missed by R&D, QA, Product Management, Marketing, Advertising, and more. Again, I just had to chuckle.

This concludes my "real-world assertion" series, and in fact my blogging with Cadence. I truly hope that you have enjoyed reading my posts as much as I've enjoyed writing them. I'll be moving on to new adventures in January. Thanks, and happy holidays everyone!

Tom A.
The truth is out there...sometimes it's in a blog.

Video: Incisive Formal Verifier R&D Leader Pradeep Goyal talks about Expert Formal Use Cases

2011-12-19T14:00:00Z

Continuing the series that introduces you to the people that create the tools you use every day, in this video R&D lead for expert-level use cases in Incisive Formal Verifier (a/k/a "IFV") Pradeep Goyal talks about the common use cases for "pure" formal users. He also notes how expert-level formal techniques might evolve over the next 5 years -- both alone, and in combination with simulation technologies.

If the embedded video doesn't play, click here.

Please feel free to ask Pradeep questions via the comments below; or click here to jump to the Team Verify home page to "send Team Verify a private message" for forwarding to him offline.

Joe Hupcey III
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Reference links to prior R&D interviews:
Distinguished Engineer Alok Jain

Incisive Formal R&D team leader Deepak Pant

Incisive Enterprise Verifier R&D Architect Vinaya Singh

Early Holiday Present: Sudoku Solver Using Incisive Enterprise Verifier (IEV) and Assertion-Driven Simulation (ADS)

2011-12-13T23:30:00Z

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present. On the Functional Verification Shared Code Forum I've just posted a ZIP file with Sudoku solver code for Incisive Enterprise Verifier (IEV). The file is at http://www.cadence.com/community/forums/T/21110.aspx

The Details:
First, we map a standard 9x9 Sudoku puzzle into a 9x9 Verilog number array with unknown (X) locations, and then apply 3 sets of PSL assertions to constrain:

a) unique numbers in rows

b) unique numbers in columns

c) unique numbers within squares

The solution is calculated using IEV's Assertion-Drive Simulation capability -- recall prior posts on how "ADS" works and user experiences -- specifically, we use the "search" command with the results shown in the familiar SimVision waveform viewer.

If the provided Sudoku puzzle has no solution the tool will report a conflict as follows:

formalverifier: *E,VACNUL: Verification cannot proceed because conflicting constraints have blocked all paths. Remodel your constraints before invoking the tool again.

formalverifier: *W,SRDEAD: The tool has encountered a deadend state. Use debug -solver -deadend command to view the conflicting constraints.

For example, if we add another numeral ‘6' in column 1 (by adding "s[1][1] = 4'd6") we will see a message highlighting the constraint in conflict with the Sudoku:

FormalVerifier> debug -solver -deadend

Deadend-state constraints/conditions

sudoku.gen_col[1].col_unique, file ../rtl/sudoku_solver.psl, line 18

To run the solver code after you unpack & install it:

% cd iev
% iev -f iev_sudoku.f

% irun -f irun_sudoku.f

Enjoy!

Joerg Mueller
Solutions Engineer
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Report on ARM Techcon 2011: Real and Virtual Software Apps, High-Speed Silicon and Lego Hardware

2011-12-13T17:00:00Z

The acid test of any conference is how long the information and lessons learned linger in your mind after the keynotes, panels, and demos wrap up. Like last year, the 2011 edition of ARM Techcon is passing the test of time. Below are some of the highlights that have stuck with me and/or have been prompted by follow-on news since the event.

This year's ARM Techcon highlighted advances on many fronts -
semiconductor tech., business models and "apps", virtual prototypes,
and record breaking Rubik's cube solving!

"The ARM v. Intel fight just got good": This headline borrowed from this short&sweet GigaOm piece on ARM's 64 bit architecture announcement hits the nail on the head whether you are talking about the mobile domain, or the less glamorous server-based processors. Specifically, everywhere you looked at Techcon there was something competitive, if not outright threatening, to "only the paranoid survive" Intel fans. Suffice to say both companies have their work cut out for them in this high-stakes competition that's unfolding at both the "macro" systems level, as well as the nanometer level (to wit: compare announcements of ARM-based 20 nm test chips vs. Intel's tantalizing hints of 14nm processes working in the lab). On this score it will be interesting to parse through the upcoming CES 2012 product & design win announcements to see how this competition is paying out.

Speaking of semi news from Techcon ...

Sub-20nm is the Rubicon: Long time followers of semiconductor technology are used to periodic "sky is falling" comments (remember the "electromigration crisis"?). However, in two different keynote speeches it was made clear that below 20nm it truly is a brave new world. First, I was struck by the blunt clarity of TSMC's CEO Dr. Shang-Yi Chiang's statement that "20nm is the last generation of planar transistor." Later that morning, Cadence's Chi-Ping Hsu's keynote titled "High Stakes at Low Process Nodes" drove home the consequences of this statement in a myriad of ways. Perhaps due to my EDA-origins, one 20nm discontinuity that stuck with me is that 20nm design adds more than 400 design rules to the layout process. Reinforcing Dr. Chiang's statement with a few simple examples of these seemingly contradictory rules, he dramatized how layout is now even more of a 3D chess puzzle than ever. As such, Chi-Ping's assertion that the "aggregate EDA tool development costs ... are estimated at $400-$500 million at 32/28nm and $800 million - $1.2B at 22/20nm" seem like underestimates, if anything.

New Avnet & ARM software store shows EDA360 in action: When long time component distributor Avnet partners with IP leader ARM to leap into the software services business, you know that the electronics industry's tectonic plates have shifted by a few yards. Specifically, the announcement of a new embedded software app store seems like it was torn out of the pages of the EDA360 vision document, where Avnet realized that there is money to be made by enabling their customers to "differentiate silicon with software" as so crisply stated by Harvey Feldberg in his keynote.

"Look Ma, no hardware" with Virtual Software Prototyping: As the many vendors writing apps for the aforementioned embedded software store can no doubt attest, the plethora of processing options and low cost of processors in general are drastically complicating the system development task. Fortunately, virtual prototyping - i.e. complete system models that enable software development and debugging before system hardware is available - took a quantum leap at Techcon with the introduction of the "Virtual System Platform" by my colleague and Cadence R&D Architect Jason Andrews. In his paper on "Creation and Usage of SystemC Virtual Platforms for Multi-Core System Debugging and Analysis", Jason showed a no-kidding case of how this new platform can simultaneously help everyone from system architects, pure software coders, and RTL developers, get the design and debug information they need in the format that they are most comfortable using. (In addition to the written paper in the conference proceedings, a video of Jason's presentation is publicly available on YouTube. Jason is an engineer's engineer, so while the video is 47 minutes it's no-hype, productive lunchtime viewing.)

Lego Rubik's cube robot: last but not least, I must again tip my hat to the world-record breaking "CubeStormer II". It's such a fun display of ARM's expertise that my product team has replicated the idea using our formal verification product as the "brain" of our own (mechanically slower) Lego robot - coming soon to a trade show near you ...

Finally, included below are some additional links to high-value ARM Techcon-related articles, blogs, and videos.

Until next year, may your power consumption be low and your throughput be high!

Joe Hupcey III

Twitter: @jhupcey, http://twitter.com/jhupcey

Reference Links

More from Richard Goering's "Industry Insights" column: ARM TechCon Highlights Roundup - Blogs, Videos, and More

Highlights from Steve Leibson, the "EDA360 Insider"

"Charbax's" (a/k/a Nicolas Charbonnier of ARMdevices.net) catalog of ARM Techcon video blog entries

Gary Smith: ARM TECHCON 2011 - The Week The World Changed
http://www.garysmitheda.com/read.php?story=iNotes_106

ARM Chips Away at Intel's Server Business!
http://www.semiwiki.com/forum/content/850-arm-chips-away-intel%92s-server-business.html

Embracing Our Competitors with the Connections Program

2011-12-06T23:00:00Z

In my last blog post, I described the Cadence Verification Alliance (VA) and how it provides value to customers, VA members, and us. I've been pleasantly surprised at the readership numbers given that this is what radio commentator Paul Harvey used to call "shop talk" when he discussed his own industry. I believe it's important for EDA users to know that their vendors and ecosystem partners put a great deal of effort into working together. We don't do this work just to sit around and sing "Kumbaya" with our competitors -- we do it because our customers need us to do it.

The truth is that very few customers have a single-vendor EDA environment. For any number of technical or business reasons they have tools, design IP, verification IP, and libraries from multiple sources. Users look to the EDA industry to reduce their integration effort by validating that products from different vendors interoperate and work well together. Virtually all EDA vendors have agreements with complementary suppliers as well as competitors, often exchanging tools so that each pair of products linked together can be validated by both vendors.

At Cadence, our EDA interoperability program is called Connections, and it's one of the largest such alliances in the industry. We have roughly 80 member companies today; that number moves up and down a bit over time as existing companies merge or fail and as new startups emerge. Scan through the list, and you'll see that we are quite inclusive. Many Connections members have products that are directly competitive with Cadence offerings, but that is not a fundamental barrier to joining the program. As noted above, we do what our customers need us to do.

The most important criterion for joining Connections is identification of mutual customers who are asking for the interoperability testing possible only when two vendors exchange tools. Sure, I would love it if every one of our simulation customers used only Cadence solutions. But that's not reality; we have some e customers who run Specman with other simulators, some mixed-signal customers who run our digital simulator with someone else's analog simulator, and vice-versa. We always try to offer a better combined solution ourselves, but that will never satisfy everyone.

Of course, there are also some Connections members whose products are mostly or entirely complementary with ours. In my series on automatic assertions I mentioned NextOp and Zocalo as examples of vendors in this space, and we recently presented a joint Webinar with Duolog. All three companies are in Connections and are fine examples of partners with complementary offerings and with whom we do joint marketing activities. If we can offer customers a broader solution by working together with another vendor, we're glad to do so.

If you haven't read about EDA alliances before, you may be surprised that we have so many of each other's tools. The agreements are carefully written so that we don't reverse-engineer our competitor's products or otherwise take unfair advantage of having them. In my dozen years in EDA, I can recall only one incident in which a partner blatantly violated such an agreement by benchmarking my company's tool against their own competitive offering. That's the exception; these alliances work because we focus on interoperability testing (only) for the benefit of our mutual customers.

So now I've shared the "secrets" of both the Verification Alliance and the Connections Program. You can read about a closely related program, the System Realization Alliance, from my colleague Steve Brown and see the complete scope of our ecosystem activities on our Web site. If you have any questions or wish to suggest additional partners or ideas for alliances, please comment. As you can imagine, we bloggers are a lot happier when we see a few comments rolling in, so don't be shy!

Tom A.

The truth is out there...sometimes it's in a blog.

Holiday Idea #1: Give the Gift of UVM Knowledge

2011-12-06T21:00:00Z

Your favorite verification engineer has been good all year. Thousands of tests run. Nights and weekends of debug. So how do reward her? Why, with UVM Training, of course!

Cadence experts have trained hundreds of engineers on OVM and UVM. These trainers have deep knowledge in both the methodology and the Incisive simulators that run it. They track the latest activities in the Accellera Systems Initiative standards committee, and the latest releases from that group, to keep their training on the leading edge. Each of the trainers avidly read and contribute to the UVM World forums to understand current issues and to share their knowledge. Whether you attend a standard Cadence UVM training class or a custom one, you are in good hands.

The course begins with a short review of SystemVerilog classes and class constructs, together with an overview of object-oriented concepts and features.

The reminder of the course describes the Universal Verification Methodology (UVM) class library, which provides the building blocks and infrastructure for a verification environment, and defines a methodology to show how the class library can be used to create powerful, reusable UVM Verification Components (UVCs) based on a standard architecture.

UVM is the Accellera standard replacement for OVM (Open Verification Methodology), a class-based verification library and reuse methodology for SystemVerilog®. UVM is supported and endorsed by almost all EDA vendors, including Cadence, Mentor, and Synopsys. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology allows engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments. It also shows how to combine multiple UVCs into a full verification environment.

Learning Objectives

After completing this course you will be able to:

Review SystemVerilog class-based features and to examine the use of dynamic class instances to create both data objects and verification components.
Explore the features and capabilities of the UVM class library for SystemVerilog.
Define and explain a clear, proven methodology for creating reusable, scalable and robust verification components.
Gain hands-on experience of how the UVM class library can be used to implement a verification environment based on the methodology above.

So if you are in a bind and your favorite verification engineer has a hankerin' to stay on the leading edge, give them the gift of Cadence UVM training this holiday season. Click here for more details.

Adam Sherer

Secrets of the (Verification) Alliance

2011-11-29T23:00:00Z

In a recent post, I discussed the need for cross-vendor cooperation in EDA, especially in my world of functional verification. It takes a blend of innovative technologies and methodologies to verify a modern system-on-chip (SoC). Customers also need training, consulting services to fill short-term needs or expand current skill sets, and providers of verification IP (VIP) for multiple purposes. As we say on our Web site, no one company can do it alone. Both the Cadence Connections program for EDA vendors and our Verification Alliance (VA) provide solutions.

I mentioned in my post that I lead the VA program, so I'd like to talk about it a bit more and discuss why many of you readers should care about this alliance. I'll start with a bit of history: the VA was started more than ten years ago by Verisity Design as a way to rally partners around their innovative e verification language. The VA contained numerous companies providing training and consulting services for e-based verification. These partners played an important role in helping customers get up to speed on the language and object-oriented programming.

One critical segment of the VA was the partners providing VIP. The SoCs that were verified with Verisity's Specman Elite tool often contained standard interfaces. Licensing robust e VIP saved customers considerable time and effort while increasing confidence in the implementation of the standards. The range of protocols required was more than any one small company could provide, so Verisity proactively built a VIP ecosystem within VA. After Cadence acquired Verisity in 2005, the focus of the VA program broadened to include companies with expertise in SystemVerilog, SystemC, and formal analysis.

Today the Verification Alliance remains very much alive and active. There are currently more than 40 members spanning 14 counties, ranging from solo consultants to some rather large firms. As the primary approver for membership, I actively seek appropriate companies and invite them to join. We typically provide a few copies of relevant products so that members can train their staffs on Cadence verification solutions. Every year we license several million dollars' worth of our products to our VA partners in exchange for a small fee.

So what do we get in return? In cases where a VA member is a product company, they may provide reciprocal copies of their tools or VIP. The VA consulting and training companies offer a trusty place to send our customers who might benefit from their services. Sure, Cadence has consulting and training services too, but we can't always satisfy every demand in every corner of the world so the VA partners are a welcome backup. As experts in their fields, many VA partners also provide feedback to help us improve our solutions for our customers.

Finally, we actively look for opportunities to work with our partners in public events, especially those reporting on mutual customer success. For example, Oski Technology gave a presentation at the Design Automation Conference (DAC) last year on a consulting project for Cisco. Using Cadence's formal-analysis tools, they successfully verified a complex statistics block in only 3 months versus the 18 months projected for simulation. As another example, when we launched the UVM World site we called on VA partners to endorse it, contribute content, and later present at the DAC UVM booth.

I could give lots more examples (AMIQ presenting at CDNLive!, joint seminars with Doulos, etc.) but I'm sure that you get the point. The Verification Alliance is an essential program with many proven benefits to customers, partners, and Cadence. It's a big deal for me, but it's just one of six major alliance programs here at Cadence. In my next post I'll pass on some information and thoughts about the Connections Program. Until then, please let me know if you have any questions about the VA program or any of its members.

Tom A.

The truth is out there...sometimes it's in a blog.

Video: Meet Incisive Enterprise Verifier R&D Architect Vinaya Singh

2011-11-29T22:30:00Z

Continuing the series of introducing you to the people that create the tools you use every day, in this video the R&D Architect of Incisive Enterprise Verifier (a/k/a "IEV") Vinaya Singh talks about the advantages of combining formal and simulation technologies, the most common misconceptions people have about mixing the two, and where this technology might go in 5 years time (preview: beyond RTL verification!).

If the embedded video doesn't play, click here.

Please feel free to ask Vinaya questions via the comments below; or click here to jump to the Team Verify home page to "send Team Verify a private message" for forwarding to Vinaya offline.

Joe Hupcey III
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Reference links to prior R&D interviews:
Distinguished Engineer Alok Jain

Incisive Formal R&D team leader Deepak Pant

Update to the OVM Register Package

2011-11-29T14:00:00Z

OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects.

The Cadence genIES team has been remiss since the demise of the OVM World, which left the OVM community to use OVM_RGM 2.5. We did try to post to UVM World, but that is really dedicated to the UVM. Therefore, we will be picking up the contribution thread and maintaining the Cadence contributions to the OVM here. By far the most popular is the register package so we are posting the latest version 2.7.1 here. We've included the release notes from 2.6, 2.7, and 2.7.1 to bring you all up to date. Of course, the complete release note history is in the tarball.

Release Notes for OVM_RGM2.7.1
Nov 18, 2011

** Bug Fixed:
¯¯¯¯¯¯¯¯¯
¤ Fixed issue with backdoor read for special read fields
¤ Fixed issue with sync for special read fields

Release Notes for OVM_RGM2.7
Sept 21, 2011

** Bug Fixed:
¯¯¯¯¯¯¯¯¯
¤ Walking one sequence did not create the regOp when writing
¤ Mode based register enum field macro having wrong case statement
¤ Typo in DPI file (vhpiHandleT changed to vpiHandle)
¤ Check for address overlap for indirect / shared and mode-based corrected

** Enhancements:
¯¯¯¯¯¯¯¯¯¯¯¯
¤ Added support for mode based registers having separate storage

Release Notes for OVM_RGM2.6.1
Aug 18, 2011

** Bug Fixed:
¯¯¯¯¯¯¯¯¯
¤ Fixed issue with syncing to VHDL
¤ Register overlap check error with end address
¤ Backdoor read of register fields was not properly masked
¤ Filtering of registers having unknown value is now only for rd_all regs seq

** Enhancements:
¯¯¯¯¯¯¯¯¯¯¯¯
¤ Allowed backdoor write to read-only fields
¤ Allowed register's reset value over-ride using plusArgs
¤ Added register array delete at the end of built-in-seq
¤ Added support field-level backdoor access for shared register
¤ Modified shared_reg_backdoor example and added ipxact file
¤ Removed all uvm deprication warnings from examples
¤ Added more support for VHDL backdoor std_ulogic_[ports|signals|vector_signals]
¤ Modified all headers of XML files to get schema from http
¤ Added objection to built-in-sequences
¤ Added a global field to mask-out comparison of all non-read-write fields
¤ Added a global field to enable warning when accessed address is outside container

=Incisive genIES Team

Video: Meet Formal and ABV R&D Team Leader Deepak Pant

2011-11-22T19:00:00Z

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer Alok Jain, while I was in India for CDNLive! I jumped at the opportunity to introduce to this community to more leaders in our R&D organization -- people that directly drive the development of the tools you use every day. Hence, in this video Incisive Formal R&D team leader Deepak Pant talks about how formal has gone well beyond basic, IP-level verification, and how the concept of coverage can extend to formal -- both for debugging formal constraints as well as for simulation-style progress measurement and coverage unreachability.

If the embedded video doesn't play, click here.

Please feel free to ask Deepak questions via the comments below; or click here to jump to the Team Verify home page and click on "Send Team Verify a private message" for forwarding to Deepak offline.

Joe Hupcey III
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

India Needs Real-World Assertions Too

2011-11-18T01:09:00Z

I've just returned from a week-long trip to India, spending most of my time at the Cadence R&D center in Noida. I was last there a year ago for our CDNLive! India 2010 event, a great show that prompted me to write a glowing blog post. This year's show was covered admirably by my colleague Joe Hupcey, which was fine with me since traveling to India twice in three weeks would be tough even for us seasoned road warriors. This time my focus was strictly on product development and deployment, topics that consumed a full week very easily.

It's amazing how much my Indian experience has changed since I had my first R&D site there 15 years ago. In those days we had a small office suite leased from a tile manufacturing company, one window air conditioner that didn't really keep the place cool, a single speakerphone shared by the entire staff, and dial-up Internet access so unreliable that we sent floppy discs through the mail rather than trying to send source code via FTP. When the power went out, typically 2-3 times a day, we would start up a noisy gas-fired generator out on the balcony.

To be fair, at the time I worked for a startup and doubtless larger companies had somewhat better offices. But today the Cadence Noida site is the peer of any in the world, not just in physical facilities but also in terms of engineering talent and productivity. I really enjoy visiting India, and our team in particular. But I didn't start this blog post just to talk about my trip. Along the way I had a few experiences that reminded me yet again that the real world seems to be missing assertions that would prevent some illogical situations from arising.

My first example occurred before I even left the ground. In the departure lounge at San Francisco International Airport (SFO), I noticed the sign shown at the right:

In case you have difficulty viewing the image, below the sign and arrow requesting "comments" are two holes and an outline on the wall where clearly some sort of receptacle for comments had once been attached. I got a good chuckle out of that, promptly snapping the photo and posting on Facebook with the comment "Apparently somebody decided that they didn't want passenger comments after all." It's almost too easy a target, but I'll assert that if you're going to remove the receptacle for comments you must remove the sign requesting them as well.

My second example occurred at a fairly new and very nice Southeastern Asian restaurant near my hotel in Noida. Of course we ate a lot of good Indian food on the trip but the menu at this place looked promising for something different. In fact the food was very good and the service quite solicitous; clearly they were looking to build a positive reputation. When the waiter brought the check I gave them my credit card, and when he returned he brought the familiar printed receipt with a line to specify the tip and a line below to indicate the total.

Since the service had been good I wanted to give him a nice tip, so I wrote in the amount and the total. He returned a few minutes later saying that the tip would not work on the card; after a few minutes of confusion we realized that they had no way to add the tip to the credit charge. This is fairly common outside of the United States, especially in Europe, but the receipt generally does not leave a space for a tip. So I left the tip in cash, but I'll assert that if a credit-card receipt has a place to write in a tip the restaurant must allow the tip to actually be charged to the same card.

My final example is a bit odd. It's a rarity on a business trip to see much of anything beyond hotel rooms and conference rooms, but my colleagues kindly arranged for a pedicab tour of Old Delhi (check out wheninindia.com - highly recommended). Several hours of visiting historic mosques, markets, and other sites led us to the Red Fort, a staggeringly impressive complex once the center of the whole Mughal Empire. As dusk was settling over the city we settled down to watch a "light and sound show" of the fort's history.

The multi-media aspect was dated, but I enjoyed a narration that filled in some gaps in my knowledge of Indian history. In one segment, the narrator mentioned a king falling in love with a woman of dubious reputation (I won't use the word here) and installing her in his palace along with her friend who had "the most luscious watermelons." I'll assert that you shouldn't use derogatory slang for women and double-entendres in a family show intending to teach history. My Indian colleagues had the same reaction so I don't think I'm guilty of cross-cultural judgment.

So that's a quick summary of a business trip that was much more enjoyable than most, and three more real-world assertion stories for you. My next blog post will jump back into more serious topics, based on a request from my last post on cooperation in EDA and verification. One of my colleagues suggested that readers probably don't know much about the Cadence partnership programs, and the Verification Alliance in particular. Unless there's some major industry change that would take priority, I will cover partners in my next post.

Tom A.

The truth is out there...sometimes it's in a blog.

Event Report: Club Formal Shanghai

2011-11-15T00:00:00Z

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and as you can see in the image gallery below 24 customers from different 6 companies came together to share their general experiences and detailed case studies on formal and assertion-based verification (ABV). We also took the opportunity to announce and demonstrate some new technologies, share our product roadmap, and learn new requirements from the attendees to better align our R&D development with their needs.

Here are some specific highlights from our information-rich agenda:

1. "Warm-up" Demo: rapid design bring-up
To give everyone some "food for thought" and seed our later conversations, I kicked off the proceedings with a brief demo on our rapid "bring-up" flow. Specifically, I showed how Automatic Formal Analysis (AFA), Assertion-Driven Simulation (see prior post and archived webinar on "ADS"), Assertion-Based Verification IP and pure formal together can shorten the cycles of designer and verification engineers to bring-up and explore a new design without testbench.

2. Incisive HDL analysis ("HAL") overview and usage with IFV/IEV
R&D's Jianxin Bai talked about the HAL technology in general, and how its linting capabilities can be used to tee up efficient IFV/IEV runs.

3. Automated SoC iIntegration verification and demo
Peng Yu showed how formal technology can be applied to connectivity verification in SoCs via automatically generated assertions, and how this methodology out-performs the traditional simulation approach on coverage and productivity. (Ed. Note: there is an archived webinar on this topic posted here)

4. Code coverage unreachability analysis with Incisive Enterprise Verifier (IEV) demo
I had the honor of presenting the newly released coverage unreachability flow, which aims to reduce the time to coverage closure by determining the unreachable code coverage automatically by formal technology, and most important it's an integrated solution to existing simulation.

5. Writer block verification using Incisive Formal Verifier (IFV)
Legang Sun (LSI) shared his experience on applying RTL checks and AFA of IFV to the "writer" block (a block shaping the write signals to a hard disk). Those automatic checks and assertions detected design issues with very low effort, thus visibly increased the team's productivity.

6. CRG block verification using IEV (Hisilicon)
Ke Xu (Hisilicon) shared his work on Clock Reset Generation (CRG) block with ABV and IEV. He spoke about the reasons for adopting formal verification on this block and how several efficient corner case bugs were caught by IEV, and also shared feedback on how to make the tool and workflow better.

7. IFV & IEV roadmap highlights
Last but not least, Product Engineering lead Axel Scherer presented the big picture of solutions we offer today around formal verification, and shared our near term product roadmap.

At the end of the day, everyone was a little overwhelmed by so much information, but in a good way. Everyone found the presentations and demos to be of immediate, "I can go back to my desk and try this right now" value; plus they gave our factory representatives lots of valuable feedback which will definitely help us to improve our solutions.

Until the next Club Formal, happy verifying!

Jin Tang
Principal Solutions Engineer
Shenzhen, China
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots!

2011-11-08T01:00:00Z

Recently I had the honor of presenting the functional verification roadmap at CDNLive! India in Bangalore. With the high quality of content and networking, it was easy to see why attendance has increased year-over-year; and why CDNLive India has become the premier conference on the region's engineering community calendar. The following video montage should give you a flavor of the event (if video does not appear, click here).

Plus, here are some additional (functional verification-centric) highlights:

* Functional verification roadmap: I was excited that our roadmap was well received, drawing questions around low power, UVM, class debug, and assertion-based verification (ABV). Note to attendees: for those of you that requested we smooth out the process of upgrading new versions, be advised that I have communicated your feedback directly to my colleagues in Product Management and R&D leadership in Chelmsford, Noida, and San Jose.

* Formal verification interest: While the Functional Verification track covered topics spanning UVM, metric-driven verification (MDV), low power, and analog-mixed signal verification, the popularity of formal and assertion-based verification paper -- 4 out of 8 papers in the track -- clearly signals formal and assertion-based verification (ABV) is breaking out of niche, expert-only usage and into mainstream design and verification flows. Colleague Lokesh Pundreeka summarizes the formal analysis papers in this recent blog post:
http://www.cadence.com/Community/blogs/fv/archive/2011/10/26/report-formal-analysis-papers-at-cdnlive-india-2011.aspx

In general, all of the papers were excellent, and I urge you to download and review all them:
http://www.cadence.com/cdnlive/in/2011/pages/proceedings.aspx

* Our Rubik's Cube solving robot: Speaking of formal verification, we couldn't resist the opportunity to introduce formal/ABV to the general assembly via a booth hosting our own Rubik's Cube robot. Leveraging a mechanical design by Lego Mindstorms wizard Hans Andersson, colleagues Apurva Kalia, Suman Ray, and Manu Chopra setup the brain of the robot to be a single SVA assertion that is solved in a few seconds by Incisive Formal Verifier (IFV). (The core program is a single SVA assertion (in a nutshell, "never (solved cube)"), which IFV solves and then produces a counter example which turns out to be the optimal solution to the cube. A script translates the counter-example signals into a set of actuator commands for the robot to execute.) As you can see in the summary video above, the demo itself was a hit and enabled us to demystify formal and ABV for many attendees in a fun way.

* Solid keynotes: Last but not least, the keynotes by our own Charlie Huang and Dr. Srini Rajam, chairman and CEO of Ittiam Systems were really thought provoking. In particular, in his talk "Designing Systems to Thrive in Disruptive Trends," I really liked how Dr. Rajam smoothly made his point via a quasi-Socratic method of delivery. Specifically, he invited the audience to consider a hypothetical conversation between a design engineer and end-customer of a consumer electronic device to make the point that to successfully manage "convergence" of capabilities you need to support successive layers of abstraction. His follow-on anecdote centered on thinking and designing "big" first, then scaling down later, nicely reinforced his main thesis.

Until next year, happy bug hunting!

Joe Hupcey III
On Twitter: @jhupcey -- http://twitter.com/jhupcey

Reference Links:
All CDNLive India 2011 papers have now been posted online. I strongly urge you to download and review them!
http://www.cadence.com/cdnlive/in/2011/pages/proceedings.aspx

Report: Formal Analysis Papers at CDNLive India 2011
http://www.cadence.com/Community/blogs/fv/archive/2011/10/26/report-formal-analysis-papers-at-cdnlive-india-2011.aspx

Cadence Announces Winners of CDNLive! India 2011 Best Paper Awards and Cadence India Design Contest
http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=102011_cdnlive

Video Easter Egg: Incisive Formal Verifier and SVA driving a Rubik's Cube robot
http://www.cadence.com/Community/blogs/fv/archive/2011/04/21/video-easter-egg-incisive-formal-verifier-and-sva-driving-a-rubik-s-cube-robot.aspx

Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar

2011-11-04T22:00:00Z

Please join Team Verify and other D&V engineers for one or both of the following free events over the next 2 weeks:

* This coming Tuesday November 8 starting at 11:30am on our San Jose campus, we are holding the next installment of "Club Formal." The main topics for this event will be abstraction and coverage unreachability methodologies. Here are more specifics: http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=617

* On Thursday November 17 at 9 am Pacific time, Solutions Engineer Joerg Muller (you may recognize him as the author of the recent "Formal Verification of Asynchronous Clocks" post) will show how the popular dynamic simulation methodology of scoreboarding can also be extended to the formal verification domain. Furthermore, as the EDA360 Insider notes, Joerg will show how we can fashion the scoreboard to be like an "app" so engineers with little assertion-based verification (ABV) experience can apply the technique. Here are more details on this free event:
http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=560

See you in San Jose, or "on the radio", soon!

Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

P.S. What's a free "Club Formal" user group event like? Here are highlights from prior events we've held here in San Jose and around the world:
http://www.cadence.com/Community/blogs/fv/archive/2011/06/28/before-dac-there-was-club-formal-an-event-series-completely-focused-on-formal-and-abv.aspx?postID=1285587

P.P.S.: What are our free webinars like? In a nutshell, they are technical deep dives by domain experts on specific topics - with code examples and everything. Plus: attendees are always welcome to jump in and ask questions of the presenter via text chat or the live audio connection. It's easy to confirm this for yourself -- all of our webinars are recorded and archived here for you listening pleasure:
http://www.cadence.com/cadence/events/pages/archive.aspx

Verification and the Need for Collaboration

2011-10-28T15:00:00Z

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better and busier every year. I was walking around the expo floor, checking out the new vendors and saying hello to old friends, when I got into a conversation with one of our more active partners. He thanked me for supporting the various activities that we have done together and said that he felt we were much more open to EDA partnerships that the "Cadence of old" (his term). He asked whether that was specific to the functional verification space or was true in general.

We chatted about that a bit, and I gave it some thought afterwards. I've been an employee, an EDA partner, or a customer of Cadence for 20 years nonstop, ever since the acquisition of Valid Logic way back in 1991. Looking back over that time span, it does seem to me that there have been ebbs and flows in the company's eagerness for partnerships. From the outside looking in, sometimes it seemed as if Cadence, then the largest EDA supplier by far, wanted to do everything themselves with minimal collaboration.

Well, that's certainly not the Cadence I've known for the past five years as an employee. We work every day with partners of all shapes and sizes: EDA, VIP, design IP, consulting, and training companies. We commit a big chunk of resources to standards activities, another vital form of partnership. The strong progress that Accellera has made on the Universal Verification Methodology (UVM) and the Unified Coverage Interoperability Standard (UCIS) would never have happened if we stuck our heads in the sand and refused to cooperate with competitors.

If you look at the Cadence Web site you'll see that we have a wide range of alliance programs that cover just about everyone in the industry. As we say on the site, "No one company can do it alone." I strongly believe this and in fact I devote a significant portion of my time to leading the Verification Alliance (VA) program and participating in other partnership and standards programs. My colleagues and I actively engage in joint marketing activities with many partners; AMIQ, Duolog, NextOp, and Zocalo are just a few recent examples.

This brings me back around to the question from my partner at DAC, and (finally!) to the title of this blog post. Indeed, I do believe that partnerships and collaboration are particularly important in the realm of functional verification. As I've said before, there is no silver bullet for verification. Chips are only getting bigger and more complex, the verification problem is only getting harder, and EDA360 requires much more soffware verification. It takes a combination of technologies and techniques all operating on a base of industry standards to provide efficient and effective solutions.

No one company can do it alone. Cadence has the broadest verification offerings in the industry, but we know that's not always enough. We will continue to drive standards, partner with companies offering complementary technologies, and work with competitors to support our mutual customers. If you see interesting new technology outside of Cadence, please let us know, and we will find an appropriate relationship to work together. Functional verification is a very tough nut to crack, and we're open to any novel kinds of hammers that may come along.

Tom A.

The truth is out there...sometimes it's in a blog.

Report: Formal Analysis Papers at CDNLive India 2011

2011-10-27T05:24:00Z

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains came together for CDNLive India 2011. Among the attendees were over 300 design and verification professionals who focused on the functional and system verification tracks. In this post I'll pull together some highlights from the customer presentations, with particular emphasis on the papers about formal, formal combined with simulation, and assertion-based verification (ABV).

Preface: prior to the event we were blessed with an embarrassment of riches. We received 12 very strong abstracts on formal and ABV-related topics from world-class organizations like LSI, Cisco, TI, NXP, STMicro, Freescale, KPIT, WiPro, NVIDIA and SanDisk that covered SoC integration, constraints validation, coverage closure, complex IP verification, AMBA-specific bus metric-driven verification using ABV IP, cache controller verification ... and more!

Clearly formal and ABV were hot topics, but the program committee needed to balance it with other major industry issues like Universal Verification Methodology (UVM) adoption, low power design and verification, etc. Consequently, our panel of judges (comprised of well known VLSI industry experts) had a very tough time to short-list only 4 formal-related abstracts along with papers covering UVM, Low Power, and high speed IP verification in the Functional Verification track.

The formal and ABV-related papers included these highlights:

* The first paper on formal and ABV was presented by Cisco Bangalore. Entitled "Formal verification or simulation? Which way: Case study on a packet parser block", this paper explained the reasoning behind their selection of formal verification instead of simulation for verification of complex IP blocks. Initially they had a few setbacks by choosing sub-optimal methodologies for formal verification. But with some coaching and experience their final approach gave them visibly better returns than prior projects. Case in point: they quickly discovered some bugs with formal that would have been very difficult to catch with simulation. The Q&A after the paper made clear that it was well received by all attendees.

* The Freescale Noida team presented a paper on an "Innovative Approach to Coverage Closure through Un-reach ability analysis Flow". This paper explained how difficult and important it is to get code coverage closure on IP and the parent subsystems. They explained how Incisive Enterprise Verifier (IEV) based coverage hole analysis flow helped them to quickly reach their coverage goals and pinpoint unreachable (dead) code for the designers. As with the earlier formal paper, this one also generated lots of visible interest, and I dare say it opened a lot of eyes to the benefits of mixing formal and simulation-based approaches.

* NVIDIA Bangalore presented "Complex IP Verification Methodology using Property Driven Simulation (PDS) in IEV and Case study on memory controller". This paper clearly highlighted how PDS (also called "Assertion-Driven Simulation") helped them in several ways simultaneously: they could define correct design constraints in much less time than before, they could overcome design complexity that was hard to process with pure formal alone (the design had over 80,000 flip-flops), and PDS-based coverage maximization techniques helped them to identify blocks for exhaustive verification. This paper enabled each and every attendee to realize how applying formal and simulation engines together can tackle significantly higher levels of complexity without worrying much about design size.

* Last but not least, TI Bangalore presented "A Novel Approach to Coverage Completeness in Formal Checks for SOC Integration". As usual the TI team came up with a provocative paper that addressed thorny questions like, "do I have enough assertion to check my SoC integration?", and, "Has every net/pin in the assertion cone been toggled to all possible values?" In short, this paper clearly showed how important -- and feasible -- it is to get 100% coverage closure on all integration checks; and conversely, how less than 100% coverage can mask bugs if you ignore what the coverage holes are trying to tell you.

Again, it's safe to say that all of papers in the track were well received by audience. However, the NVIDIA paper "Complex IP Verification Methodology using Property Driven Simulation (PDS) in IEV and Case study on memory controller" received Best Paper Award in the functional verification category. In talking with the judges and attendees after the event, they were most impressed how the innovative combination of formal and simulation could provide so many benefits for the given effort.

Finally, if you attended the event, on behalf of all my colleagues at Cadence please accept my thanks for your active engagement! An archive of all the papers will be posted shortly on http://www.cdnlive.com/

Warm Regards,

Lokesh Pundreeka
Technical Field Leader
Cadence India, Bangalore
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Come See How to Connect SystemVerilog and SystemC Using UVM

2011-10-18T19:47:00Z

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20.

Cadence pioneered efforts to connect a major methodology across multiple languages in 2009 with the release of OVM multi-language support. We updated that again for the Accellera UVM 1.0 EA and we will be keeping that up-to-date with on the UVM World contributions page. While our contribution is not part of the Accellera standard, it is a response to many user requests. For example, we just received one this week in our functional verification forum. Even users of competitors' simulation solutions are seeking out our multi-language capabilities.

The webinar content is dominated by technical material describing the open source solution. We'll lead you through the overall requirements as we've collected from users and the solution we have availble for general use. Phu will also show how the solution applies to a realistic example and, if we have time, demonstrate that solution. There will be time during the webinar for you to ask questions to tap into the oceans of experience Phu has with SystemVerilog and SystemC. Sorry, I just had one more pun in me.

The seminar is will be held Thursday October 20, 2011 at noon EDT and you can still sign-up here: www.cadence.com/cadence/events/Pages/event.aspx?eventid=558

=Adam

Too Many Missing Real-World Assertions?

2011-10-14T22:56:00Z

Well, here I am embarking on my fifth post in which I point out illogical situations I'm come across in my daily life and suggest that the real world is missing some useful assertions. What started out as a fun way to fill a blog post has turned into a series that has received a lot of positive feedback and, as I mentioned in my most recent post, plenty of page views. I'm beginning to wonder if I'm beating this idea into the ground but I have faith that you, the readers, will comment and take me to task if you're getting tired of this topic.

In my previous set of examples, I complained about how much Web content is not date-stamped or datelined in any way. It is ironic that this wonderful medium for real-time updates so often has outdated content. Here's another example of that irony: online business listings. Physical phone books with "Yellow Pages" were (and some still are) published once a year. The Web offers many sites that list businesses à la the Yellow Pages, but with the ability to do an instant update when a new business starts or an existing one closes. That should be an improvement, yes?

However, any search will find many such sites that are terribly outdated; this one in its second paragraph plugs a San Jose donut shop that closed in mid-2006. Of course, such sites rarely have any dates to alert that they're dusty. At least with the physical Yellow Pages you knew whether you had the latest book and would never be consulting listings five years of date. Many sites have this problem but some, Yelp in particular, do a good job of noting when a business has closed. Assertion: if you have a Web site, date your content and keep it as updated as you can.

My second example occurred a couple of weeks ago at the Hardly Strictly Bluegrass Festival in San Francisco. I could go on and on about this free annual event; it's in its eleventh year and now up to 3 full days, 6 stages, and 90 acts. I was at the "Towers of Gold" stage enjoying some bluegrass from Ricky Skaggs when a young woman asked me who was playing. I answered "Ricky Skaggs" and she looked dubious. One of her two companions asked someone else and received the same reply, at which point she started juggling her festival map.

As she turned her map every which way, she kept insisting that "This can't be Ricky Skaggs because he's at the Towers of Gold stage." I said "Trust me, this is the Towers of Gold stage and that is Ricky Skaggs." She just kept pointing west and insisting that there was another stage over there. Never mind that there was an eight-foot high multi-sided sign that said "Towers of Gold" next to us; the three of them headed off toward the Polo Fields. Assertions: if you can't read a map, ask someone who can and if you ask someone for help, pay attention to the answer.

My final example involves the all-too-familiar scenario of dealing with a utility customer support line. I wanted to make some changes in my cable service that would entail upgrading my set-top box. I read all the information on the site and then started a chat with one of their customer service representatives. He was helpful enough, although he couldn't provide a delta list of channels between two tiers of service. I didn't feel like manually comparing the lists so I pasted them into two files, sorted them and ran "diff" courtesy of Cygwin.

The only hitch was that the checkout process said that I had to pick up the new box at a Best Buy store 25 miles away. The rep said he couldn't change that, and to expect email with instructions on pickup. By the next day I had received no such message, so I started another chat. Here's an abbreviated version of the chat transcript:

Rep > May I ask what specific changes being made in the account, Thomas?
Thomas > Yesterday I changed over to a new package and I was told I would receive a confirmation email with instructions about picking up my new set-top box
Thomas > I have not received such an email
Rep > Normally, we only send emails for installation or tech appointment confirmation, Thomas.
Rep > You can actually go to your local office to swap the box or you can have it via mail, Thomas.
Thomas > Can I go to a local service office? The online instructions said that I had to go to a Best Buy 30 miles away...
Rep > I am afraid to say that it could be a spam, Thomas.
Thomas > No - it was a form on your site
Rep > Okay, actually you can go directly to the local office to have your box swapped, Thomas, just bring a valid ID with you.
Thomas > OK, I will take the old unit to my local COMCAST service center as you suggest. Thank you for your help!
Rep > You are most welcome.

So the second rep told me that they never send email for equipment exchanges (the exact opposite of what I read on their own Web site) and that I could do the exchange at my local service center in San Jose (the exact opposite of what the other rep told me). Assertion: if you provide customer support, have one consistent set of information available to your customers and all your reps. Please comment if you have any such stories of your own to share.

Tom A.

The truth is out there...sometimes it's in a blog.

Formal Verification with Asynchronous Clocks

2011-10-13T20:00:00Z

Many designs have multiple independent clock inputs with different frequency specifications and/or different frequency ranges. In simulation based environments we see regressions run with randomly varying clock phase timing parameters to cover the many possible combinations. A simple Verilog example might look like:

initial begin

clk = 0;

forever #(RANDOM_PERIOD/2) clk = !clk;

end

In the formal world we can also specify the clocks as discrete crank based waveforms, using Tcl commands which allow for verification of varying clock ratios and phase relationships.

Figure 1: Clock Waveform Specification in IEV

Unfortunately, both approaches only cover a subset of all possible clock waveforms -- in effect, they represent over-constrained environments (recall Team Verify's prior post on over- constraining). Thus, for the purpose of hunting corner case bugs in the clock synchronization logic we need a more aggressive, "under constrained" approach for the clock waveform specification.

A quick and slick solution is to simply leave the clock pins completely free as randomly toggling inputs. In Incisive Formal or Incisive Enterprise Verifier we can achieve this by omitting the Tcl clock constraints above and adding "clock fairness constraints" instead. Here is a PSL example:

clk1_toggles: assume always eventually! (rose(clk1));

clk2_toggles: assume always eventually! (rose(clk2));

This will create completely unrelated clock frequency and phase relationships, modeling any possible glitch and hazard scenarios you can imagine. However, since this is an aggressively under constrained environment it might work too well and you may face failures due to extreme, illegal clock waveforms. Still, since this is so easy to setup and run, it is usually an acceptable price for exhaustive scenario coverage in a single formal run.

Surprisingly many counter examples come with pretty regular clock shapes for at least one clock, since it is in the interest of the formal engine to provide a short trace, which requires clocks to toggle.

Figure 2: Screenshot of asynchronous clock waveform using assertion driven simulation

The point is that you can bracket the clock waveform verification with the most conservative and most aggressive approaches. Specifically, we recommend the following 2-staged approach to verify designs with independent, asynchronous clocks:

1) Sync: Fixed simple (equivalent) synchronous clocks to flush out all bugs unrelated to clocking issues

2) Async: Unspecified clock waveforms to target bugs related to clock frequency, phase and glitch issues

Note that there are also approaches in between these extremes, which try to keep the clocks within a range using counters and auxiliary logic. But they come with a higher price since complexity is more likely to explode with such clock generating networks. Hence, we do not recommend such methodologies unless they are absolutely required.

Happy clocking!

Joerg Mueller
Solutions Engineer
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Automating UVM to Tackle Insidious HW/SW Bugs

2011-10-10T18:21:00Z

You've just sat through a 2-hour program review. The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying. Of course, the hardware and software reviews were boring. Blah, blah, blah about design trade-offs with some buried references to register APIs. Your metric-driven verification (MDV) plan completely covers the spec, so you are sitting pretty. Or are you...

Duolog and Cadence are hosting a webinar on October 11, 2011 at 9a PDT / 5p CET to discuss what happens if you don't pay careful attention, and how to correct that. Specifically, those design trade-offs that occur during the life-cycle of all projects often lead to changes in the API between the verification, hardware, and software domains. The verification environment is constructed, in part, to understand the bit fields in the registers that make up the API. If the tradeoffs change the bit fields in any way, the verification environment must change as well. The biggest issue is that the changes must be communicated and recognized among the team members in each domain. We all can point to cases where one team makes a "simple" change that has an unexpected impact on another.

Automation can help solve this problem. Attendees to the webinar will hear a clear description of the problem, the UVM register-package that provides a framework for the solution, and a novel technology suite that automates that solution. Led by Duolog's CTO, David Murray, the webinar will also include a demonstration of how these insidious bugs can slip through and how the Duolog solution automates the elimination of those bugs.

For more information and to register, go to http://www.duolog.com/webinar-automating-uvm-to-tackle-insidious-hwsw-bugs/

=Adam Sherer, Cadence

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal and Emulation

2011-10-05T16:45:00Z

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology for uncovering corner-case bugs, exposing functional coverage holes, and increasing verification observability. HOWEVER, there is often one teeny-tiny issue that inhibits its wider adoption: hand-writing assertions can be a real pain. To overcome this obstacle, assertion synthesis technology has emerged that enables rapid proliferation of ABV by automating the painful process of creating meaningful white-box assertions and functional coverage properties with sufficient capacity to handle complex SoC designs. Without writing any additional code, this technology can help you find additional bugs and improve functional coverage, integrating into your metric-driven verification (MDV) flow.

Great stuff -- but how does it work in reality? In a free webinar this coming Thursday October 13, 2011 at 9am Pacific, Team Verify partners with our friends at NextOp Software to show how assertion synthesis works in the real world. In addition to a live demo to reinforce the concepts introduced, we'll review in detail recent case studies from customer projects.

... and see you on the radio soon!

Team Verify and NextOp

P.S. Curious about the technical presenter, Yuan Lu of NextOp? As the CTO of a smokin' hot EDA company, he is great at dividing his time between internal development and meeting with customers. Hence, I suspect webinar attendees will recognize his voice from industry events like DAC and DVCon. For example, here is an interview that Team Verify's editor Joe Hupcey III did with Yuan back at DVCon:

If the video fails to play, click here.

A full blog post on this interview is available here.

Amazon’s New Kindles: More Steps Toward the Paperback Computer

2011-09-28T20:00:00Z

While I understand that a new Kindle Fire at $199 MRSP is significantly more than a dime novel, I assert that today's launch of the new Amazon tablets takes us one step closer to the "paperback computer" becoming a reality. Here the term paperback computer isn't just a clever play on words regarding the bookish seller of these devices. Instead, it's a reference to a conjecture introduced in 1992 by the venerable PBS series "The Machine That Changed the World". (Yes, a 19 year old reference - just bear with me for a paragraph ...)

You may recall that this series was a comprehensive documentary on the history of computing and information science, and that it also made some impressively accurate predictions of computing's future. Specifically, Episode 3, literally titled "The Paperback Computer", opens with a tour of a historic "chained library". The books in this library -- both handwritten by monks, and mechanically printed by "gen 1" printing presses -- are literally chained to the shelves to prevent theft.

The narrator goes on to state that because books were so expensive to create, "[at the time] the idea that regular citizens would own books was ludicrous." Pausing for a second to let the viewer chortle in self-congratulation that they already owned a Macintosh, IBM PC XT, or Amiga, the scene shifted to a contemporary university library where all the computers were chained to the desks to prevent them from walking away. The point was well made: while in 1992 computers had become personal, they were still expensive enough that they needed to be locked down.

Fast forward 19 years, and I assert that today's launch of the new Kindles shows the paperback computer is close at hand since the Kindles enable instant access to Amazon's complete catalog of media, and the embedded wireless connection lets users roam free from any chains. Plus: at $199 it's not the end of the word if the device gets lost, damaged, or stolen. (Of course, the device itself is not the $9.99 range of an "I won't be heartbroken if it gets lost" paperback book. Indeed, I predict that over the next ~5 years there is much revenue to be harvested -- or at least costs recovered -- from hardware sales before we see a return to the old cellular contract model of a free device with an N year subscription.)

But what does all this mean for our industry? By coincidence, the implications for EDA are well spelled out in a recent post by "EDA360 Insider" Steve Leibson that reviews a bold article by EDA-focused venture capitalist Jim Hogan. Hogan persuasively argues that EDA must enable customers to make sure "the user experience is never compromised." This boils down to enabling true SoC design, where:

"SoC 3.0 software is king and programmability is the key, a departure from the hardware-focused era of gates-and-switches chip design. Application software defines the differentiated value of the system for the consumer."

In a nutshell, as Steve Leibson meticulously documents in his review, these new mobile devices are all effective representations of the EDA360 vision of "System Realization".

The good news is that I believe Cadence and other industry players are well positioned to help customers make this transition. Speaking for Cadence, witness our parade of deliverables in this space - the Virtual System Platform, Rapid Prototyping Platform, Palladium XP, Hosted Design Solutions (a/k/a EDA-optimized cloud computing), and the new Verification IPs for emerging mobile standards announced just this week.

That said, I think "we" (Cadence and the industry) still have a have a long way to go before we completely internalize this sea change. And if we fail to stay ahead of these trends, the consequences could be quite extreme. Specifically, the Hogan article warns that external forces could even force the EDA industry to go back to the future and return to the foundry-owned ASIC tools model of the 80's and 90's (yikes!) Thus the question going forward is whether we can evolve our businesses deeper into the systems domain beyond the steps we're taking today. Time will tell, so for now I welcome you to speculate along with me in the comments below, or 1:1 offline.

Joe Hupcey III

On Twitter: @jhupcey -- http://twitter.com/jhupcey

P.S. To put a finer point on the paperback computer end state:
The central premise of this idea is that the device becomes so cheap that you really don't care if it gets lost. Consequently, assume for the moment all the data you do care about is safe inside some secure cloud computing area. As such, only the loss of physical device itself is at issue and/or local storage will be mirrored in the cloud and wiped from the device remotely in the event of loss. Further set aside the classic "free phone with contract" subsidized business model for a moment.

Hence, what is the ultimate COGS target for a $9.99, "I don't care if it gets lost" paperback computer? A cursory internet search of vanity publishers turned up the following: 10,000 units of a self-published, standard 288 page 5.5"x 8.5" paperback book, with a single color laminated cover, costs around $1 per unit. To say the least, the EDA industry, IP creators, and system integrators sure have our work cut out!

Reference Links
Amazon's new tablets

EDA360 Insider: What's unique about the new $199 Android-based Amazon Kindle Fire tablet?

EDA360 Insider: "Jim Hogan coins "Jobs' Law" and nails it to the door of System and SoC Realization"

Jim Hogan: "Job's Law"

The EDA360 Vision

Technical Tip on How to Use HDL Assertions in e

2011-09-28T17:00:00Z

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage.

ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification. HDL assertions help to detect more bugs earlier in the process and closer to their source.

This feature enables the integration between the HDL assertions and the verification environment in e by providing a simple API. The e API provides methods to enable call back registration, control and query of HDL assertions that are defined in the RTL.

Registering a callback for an HDL assertion can be done by the following simple steps:

Defining an assertion callback function:
- Derive your callback struct from hdl_assertion_cb, and implement a callback method
Calling to one of the methods which register a callback on an assertion instance:
- register_regexp_cb() - Registers a callback with the assertions that match a regular-expression input string
- register_asserts_cb() - Registers a callback for assertions list input

There are also API methods to obtain information about the assertion attributes and to enable/disable assertion checking in the simulator.

Here are a couple of examples that demonstrate how to use the API:

Registration Callback example:

Assume you have the following assertion:

property p1;
@(posedge clk) event1 |-> ##3 event2;
endproperty

assert_p1 : assert property(p1);

This example shows how to register a failure and success callback for this assertion:

Define callback methods for failure/success:

Derive your callback struct from hdl_assertion_cb, and implement a callback method that will be executed whenever any assertion fires.
. sva_cb_err will be used when assert_p1 failed.
. sva_cb_suc will be used when assert_p1 succeed.

struct sva_cb_suc like hdl_assertion_cb
{
    callback(assert : hdl_assertion) is {
            //do something
    };
};

struct sva_cb_err like hdl_assertion_cb
{
     callback(assert : hdl_assertion) is {
             //do something...
     };
};

Registering callbacks on the assertion instance:

Create instances for the callback structs in stage 1.
Use the assert_mgr method register_regexp_cb to register callbacks with the assertions that match the "*.assert_p1" input string.
(assert_mgr instance provides methods that let you define assertion instances as hdl_assertion types, and register callbacks on them)

run() is also {

var sva_cb_success: sva_cb_suc = new;
var sva_cb_error: sva_cb_err = new;

compute
assert_mgr.register_regexp_cb("*.assert_p1",sva_cb_error,FAILURE,SVA);
compute
assert_mgr.register_regexp_cb("*.assert_p1",sva_cb_success,SUCCESS,SVA);
...
};

Query example:

At run time, when the callback() function is called, its hdl_assertion argument represents the assertion within the RTL that fired. The output from the callback() method can be customized according to the users needs. For example, you may want to customize the behavior to output the assertion attributes and state of the target assertions.

The following example show an example of how to query an instance for it's attributes and state:

struct sva_cb_err like hdl_assertion_cb
{
     callback(assert : hdl_assertion) is {
          out("Assertion name : ",assert.get_instance_name());
          out("Assertion instance path: ",assert.get_instance_path());
          out("Assertion failure count : ",assert.get_failure_count());
          out("Assertion reason : ",assert.get_cb_reason());
     };
};

Control Example:

This example shows how to get all assertions in the design and then disable/enable assertions checking in the simulator.

The find_assertions method can use either a specific instance name or a regular expression to find a group of assertions. If the input string is NULL or *, the list will contain an hdl_assertion for every supported assertion in the design.
The disable_assertions/enable_assertions methods; disables/enables all of the assertions in the list.

          verify()@clock is {
               var assertions_list:= assert_mgr.find_assertions("*");
               assert_mgr.disable_assertions(assertions_list);
               wait [5]*cycle;
              assert_mgr.enable_assertions(assertions_list);
            ....
           };

Hope you found this helpful!
Michal Nevo

Missing Real-World Assertions in Computer-Land

2011-09-26T16:00:00Z

I was reviewing the page view statistics on the Cadence Functional verification blog and noticed that my previous three posts about missing real-world assertions are among the most read. So, in the spirit of milking the cash cow, I've collected a few more incidents that amused me with their utter illogic. My examples this time all have to do with some aspect of computer programs or Web sites being out of sync with the times in which we live.

As a member of several airline frequent-flier programs, I receive lots of email about travel-related sites and offers. I recently received an invitation to something called the "SkyGuide Executive Privilege Club" from American Express. It caught my attention because it promised reimbursement for one-time stays in airline lounges. Most frequent travelers are members of one airline club but there are times when its lounge is not convenient. Non-member "day passes" tend to be quite expensive, so the prospect of someone paying for those sounded good.

I went to their site and perused the details of the offer. Most of the benefits were the usual sort of vague "services" and discounts that are hard to value. But digging down a bit I found "SkyGuide Executive Privilege Club members who purchase one-day guest passes at any health club or airline-run airport lounge will receive a reimbursement for their visit." That still sounded good, until I read "Mail us your receipt via certified mail within 30 days of use." Certified mail? Seriously? What century are we in?

My second example is one that I see frequently in the Microsoft Outlook client I used to read my email at Cadence. When I sort an email folder by message size, it groups them into the following rather amusing categories:

Size: Enormous (> 5 MB)
Size: Huge (1 - 5 MB)
Size: Very Large (500 KB - 1 MB)
Size: Large (100 - 500 KB)
Size: Medium (25 - 100 KB)
Size: Small (10 - 25 KB)
Size: Tiny (< 10 KB)

I'm sure you can see where I'm going with this. When was the last time you considered a 100 KB file "large?" I have lots of Microsoft PowerPoint files with only three or four slides that consume more than 500 KB. The average MP3 audio file is several megabytes, so by Outlook's definition most of us have thousands or tens of thousands of "huge" files on our systems. I'm using Office 2007, but these categories were just as outdated in 2007 as they are now. I'm not sure I see any reason to include adjectives at all, but I chuckle every time I sort mail by size.

This reminds me of the common observation that many of the icons used in computer programs are anachronisms: desktop telephones, old-fashioned broadcast microphones, 3.5" floppy discs for "save" and so on. It is ironic that computer software-as modern an invention as any-so often hangs on to outdated terminology and iconography. But this is not an original observation so it doesn't count as one of my examples. Type "outdated icons phone floppy" into your favorite search engine for lots of entertaining commentary on this topic.

My final example is Web sites that don't date-stamp much of their content. In the early days of the Web could look at the HTML properties to see when a page was last modified, but these days just about all Web content is dynamically built so that doesn't work. I ran into this just recently when I was helping my Accellera colleagues collect links to refresh the UVM World site. I was searching the Web for recent UVM articles, papers, presentations, etc. I was amazed at how many publications and blogs didn't have a clear dateline.

Here is just one of numerous examples I found. If you happened upon this article via a Web search as I did or if someone sent you the URL, you would have no idea when this article was written. That's important to know since technology changes very quickly and the date may help you decide whether to read or skip a particular page. By looking around elsewhere on the sites I was eventually able to find original publication dates for all of the links of interest but it took significant extra effort. If this sort of thing bugs you, too, please comment!

Tom A.

The truth is out there...sometimes it's in a blog.

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

2011-09-19T18:00:00Z

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly for mobile computing applications. Customers tell us that's because it provides multiprocessor support and hardware based coherency while consuming only a small amount of power. In our experience the majority of A15 designs are also adopting the new ACE protocol due to their need for a fast and reliable coherency scheme.

To help potential A15 designers learn more about ACE, ARM and Cadence partnered to develop a video about ACE and ACE verification. It's only about 10 minutes long -- I encourage you to view it. In addition you can see my previous blog discussing the need for hardware based coherency.

While ACE compliance is challenging to verify, the even bigger verification challenge is ensuring the design is actually coherent. This is where Cadence's complete ACE verification solution provides superior value. We are seeing that nearly all ACE designs also incorporate fabrics such as ARM's CCI-400 and/or NIC-400. For this type of design it's necessary to have three verification tools all working in conjunction:

ACE Verification IP
Interconnect Monitor
Intelligent ACE Scoreboard

Only by having the ACE VIP, Interconnect Monitor and Scoreboard working together can you be assured of achieving end-to-end design coherency. Cadence's solution addresses all the common ACE/coherency verification challenges. For example it will:

Create the necessary scenarios needed to mimic processor and memory behavior including snooping operations
Ensure data coherency (i.e. ensuring that only one copy of any data is valid)
Ensure that all simultaneous write/snoop combinations are managed correctly
Ensure no scenarios create deadlocks

You can open the video below or click here to view:

For more information about ACE verification we encourage you to contact your Cadence field representative. You can also view our AMBA VIP information page. You'll find a datasheet there as well.

Pete Heller

Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up

2011-09-19T15:00:00Z

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications of "Assertion Driven Simulation (ADS) in the Wild". In the following tech tip, allow me (Chris Komar, right) to focus on a common thread through each of her stories: the need to quickly bring-up a design without having to write any throw-away RTL code. One neat trick that supports this is a handy capability in Incisive Formal and Enterprise Verifier tools ("IFV" and "IEV") nicknamed "show me", where you can set up the tool to click on a signal in the source code viewer, and then have the tool display a cover witness trace for it.

Specifically, you can quickly select a signal in your DUT and ask IFV/IEV to show the signal becoming active. Thus, instead of having to write a testbench and figure out the proper stimulus to assert the signal, you just ask IFV/IEV to show you it going active -- hence the "show me" nickname.

Without exception, every customer that I've introduced this "show me" trick to wants to use this feature, and ideally automate its operation. Hence, here is how you can map this capability to its own button on the IFV/IEV GUI for quick access.

1 - Right click in the blank space of toolbar of the IFV/IEV window to open a pop-up menu to modify the toolbar settings. Then click the "Customize" button in the pop menu to bring up the "Customize Toolbars" dialog box.

2 - In the "Customize Toolbars" dialog box that appears, click "New Toolbar" to create a user defined toolbar called "User Toolbar", then click "New Button" to open the "Create a New Button" window.

3 - In "Edit a Button" window, configure and input the Tcl script as the following figure and click "OK", which will create a new user button called "Witness Signal" in the IFV/IEV window.

4 - Next, go back and bring-up the source code browser to select a signal, then click on your new button to have IFV/IEV show a waveform that asserts that signal (which in effect utilizes the dynamic/interactive property creation via Tcl). This waveform will honor the constraints defined by your assertion.

Happy "Showing"!

Chris Komar
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

2011-09-15T13:00:00Z

Our friend and fellow blogger JL Gray recently published a post with the provocative title "UVM and the Death of SystemVerilog." That sure raised some eyebrows here at Cadence and elsewhere, leading to a flurry of tweets debating several of JL's contentions. I was tempted to join in the fray, but as I re-read his post and thought more about it, I realized that I had enough to say to write a blog post myself. JL made a number of statements that got me thinking, and while I don't intend to write a point-by-point response I do have some contentions of my own.

JL's main argument is that the virtues of a standard methodology (UVM = Universal Verification Methodology) built in a standard language (SystemVerilog) are being compromised because both are hard to learn. I can't really argue but I think it's worth separating two aspects of that difficulty. SystemVerilog is, in truth, a bit of a "Frankensteinian" language. Its many new constructs on top of Verilog came from several different sources. Further, it is a dual-purpose language meant to both describe designs and verify them. It lacks some of the elegance of certain other languages but it does the job, as evidenced by its wide usage and overall success. It is most surely not dying.

The second difficulty in learning the UVM and SystemVerilog is the leap in thinking required to embrace object-oriented programming (OOP) and other advanced concepts. This same challenge exists for just about every "modern" language as well as alternative verification and modeling languages such as e and SystemC. JL calls out for the industry to start looking at "other languages and development frameworks." I frankly find it hard to imagine that any other approach would not entail the use of OOP and therefore require a solid understanding of this programming discipline.

JL concludes by contending that EDA vendors will not, or perhaps cannot, produce the level of innovative thinking to define such a new language. His implication seems to be that both SystemVerilog and the UVM were foisted on the industry by EDA vendors and that's the best we can do. In fact, both of these were produced by standards bodies comprising a mix of EDA vendors, consulting companies, semiconductor suppliers, and systems houses. All can claim credit for the wide success of the UVM and SystemVerilog, while sharing a bit of blame for the less elegant aspects of the language.

I believe that UVM does represent innovation on the part of the industry as a whole, with EDA vendors playing a key role. The UVM has done more than any other single technology to move countless thousands of users to advanced verification. The upcoming Unified Coverage Interoperability Standard (UCIS) is another innovative industry-wide effort likely to have great benefit for users. There are many additional examples of ongoing EDA innovation in functional verification: low-power flows, much faster mixed-signal simulation, multi-core support, unique blends of simulation and formal techniques, and more.

But innovation does not imply that we need to rush off and define yet another language. Sure, someday there will a better verification language than SystemVerilog and a better methodology than the UVM. However, the reality is that every new language and methodology requires a huge investment. It takes EDA vendors three or four years to implement a new standard and by that time there's probably a new version ready to be implemented. Users invest billions of dollars in training and building reusable verification components. Let's leverage this investment; there's a lot of headroom for improved verification productivity and quality with what we have in hand today: SystemVerilog, e, SystemC models, and multi-language UVM. Let's run with it!

Tom A.

The truth is out there...sometimes it's in a blog.

Everything New is Old … Everything Old is New

2011-09-09T21:05:00Z

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl) on which several classic doo-wop groups performed versions of then-current songs. It's achieved a bit of cult status since Joey Ramone contributed a song called "Doreen is Never Boring" that, as far as I know, Ramones themselves never recorded. What the heck does this have to do with functional verification? Well, I was reminded of this title by a recent blog post from my colleague Adam Sherer about the persistence of gate-level simulation.

Adam's observations were triggered by a blog post from Ann Mutschler that specifically discussed verification of low-power design structures. She commented "in a small sense, what's old is new" in regard to the use of gate-level simulation for low-power verification. Adam's quote of her comment is specifically what reminded me of the album title, but it also led me to think a bit about some other "old" EDA tools and techniques that show no signs of going away and thus seem to be perpetually new.

There was certainly a time when many in the industry felt that gate-level simulation would go away. As I noted in my most recent post, early logic synthesis users ran lots of gate-level simulations to cross-check the synthesis process. Once RTL-to-gate logical equivalence checking (LEC) became available, the amount of gate-level simulation dropped significantly. However, it never went entirely away since patterns destined for chip testers generally had to be simulated at the gate level with full back-annotated post-route timing.

As Adam and Ann noted, gate-level simulation is even enjoying somewhat of a comeback. But it's not the only "old" technology still around. What about LEC? There used to be talk about "correct-by-construction" logic synthesis that would always create gates true to the RTL so that cross-checking would no longer be needed. There was also a notion of correct-by-construction place and route, so that such techniques as design rule checking (DRC) and layout-versus-schematic (LVS) comparison would not be needed either. Well, none of those tools shows signs of disappearing anytime soon.

Coming back up to functional verification, the advent of constrained-random stimulus generation seemingly spelled the death of manually written directed tests. In truth, many project teams still do write some tests to exercise known corner cases that may be hard to hit automatically. What about simulation itself? As formal analysis gained in popularity there was some speculation that it would replace simulation entirely. However, capacity limitations and the challenges of specifying all intended behavior in the form of assertions have kept formal in use mostly on portions of a design, but rarely on an entire chip.

I'm sure that I can think of some more examples, but this seems like the ideal spot to stop and solicit comments from you, the readers. What EDA tools and technologies did you think would be obsolete by now? What other examples can you recall where the predictions of the "experts" turned out to be wrong? What's "old" but "new again?" What's advertised as "new" but really just a rehash of old technology? I'd love to hear your thoughts!

Tom A.

The truth is out there...sometimes it's in a blog.

Can Your Verification Survive “Boot Camp”?

2011-08-24T13:00:00Z

In Silicon Valley there is a popular fitness program called "Boot Camp" where people volunteer to be run through rigorous exercises by a demanding instructor, analogous to what armies around the world do bring new recruits up to the desired physical fitness standards. Team Verify has a similar "boot camp" program where we rapidly train engineers in Formal and assertion-based verification (ABV) techniques. Like the fitness-oriented boot camp, even people who thought they were in shape before arriving to camp come away impressed, and sometimes humbled, at what the program reveals in themselves and in the blocks and systems they are verifying -- or thought were already verified.

Consider a recent example at a Formal verification boot camp held at a customer in Asia. The client gave us several existing IP blocks to use for training -- familiar blocks were chosen so the focus would be on learning some new Formal and ABV methodologies, and not on having to decode the function of the block itself. As such, expectations for finding bugs were relatively low since all of these blocks had been thoroughly verified by dynamic simulation techniques. Additionally, some IP blocks were from a trusted 3^rd party providers, and some were already taped out and in production.

However, within the week of training, previously undiscovered bugs were found in all of the blocks! Specifically, 10 bugs were found in the 4 selected designs, which came as a big surprise since they were all pre-verified by simulation. In parallel, the engineers learned the whole Formal and ABV flow: from planning and verification strategies, how to target focus areas, and assertion coding.

The moral(s) of the story:

The engineers learned Formal and ABV on real designs, making the experience personally meaningful, and economically important given the number of new bugs they found.

Even if your simulation-oriented verification is in good shape, Formal and ABV boot camp can build on this foundation to get your verification all "diesel".

If holding an ABV boot camp at your site is of interest to you, please contact your local Cadence Field office, or reach out to Team Verify via the "Contact" link at the top of this page to get in shape today!

Happy Verifying!

Jin Tang
Principal Solutions Engineer
Shenzhen, China
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

What Does SystemC Mean for Design and Verification?

2011-08-23T13:00:00Z

My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the title, my immediate reaction was to write a complementary post called "SystemC Cannot Be an Efficient Abstraction Level without IP!" This caused me to think some about the industry momentum toward using SystemC rather than traditional RTL as a design language. I chose a more general title because there are three key points I want to hit.

My first comment is that I agree with Jack's conclusions. Because C-to-Silicon Compiler's high-level synthesis can transform the same design description in different ways for different applications, SystemC IP is inherently more reusable that RTL IP. I also agree that SystemC can deliver a significantly higher level of abstraction than RTL. Sure, it's possible to write a SystemC design description that's nothing more than RTL in another language, but with training designers can learn how to write untimed, high-level code that enables boosts in abstraction and reusability.

Given the advantages of SystemC-based design, why is it not yet universally adopted? I believe that it's valid to draw a comparison with the rise of RTL-based design in the early 90s. I was a pioneer in that transition, taping out in 1989 what I believe was only the second chip anywhere using a commercial logic-synthesis tool. RTL for simulation and modeling had been around for a number of years previously, but the availability of logic synthesis was the key driver for RTL replacing gate-level schematics for design input.

There were other enabling technologies, including RTL-to-gates equivalence checking, RTL-based design rule checkers, and the availability of commercial RTL design IP. Being able to license proven design IP for a wide array of standard interfaces was a good reason to move to RTL if not already there. Even "star IP" providers such as ARM began offering RTL versions of their cores. My second main point, and the complement to Jack's title, is that the availability of SystemC design IP will be a strong incentive for designers to move up from RTL.

I say "will be" because I don't see a lot of SystemC design IP out there yet. I searched the ChipEstimate site for the keyword "SystemC" and found only a half-dozen listings, several of which appear to be RTL designs with SystemC simulation models. I have little doubt that this will change; logic synthesis was around for several years before the RTL-based IP industry made a significant impact. I expect a similar "chicken and egg" effect with the adoption of C-to-Silicon Compiler and the availability of SystemC design IP.

My final topic is what the transition from RTL to SystemC design means for my world of functional verification. Today, many SystemC designers perform the bulk of their verification at the RTL level, using the output of high-level synthesis. Again, there is a clear comparison with the early days of RTL design, when designers still ran lots of gate-level simulation. This changed over time, and likewise I expect that verification will become more and more centered on the SystemC design description.

Cadence has done a lot of work to ensure that this transition will be painless for our customers, including:

Extending the Universal Verification Methodology (UVM) to include SystemC models, including SystemC verification IP (VIP) components
Ensuring that the same UVM testbenches running in Incisive Enterprise Simulator can be used for both SystemC and RTL designs
Using the same underlying technology in SystemC testbench simulation and in the Cadence Virtual System Platform to ensure consistent behavior

I'll defer to my colleague Jack to forecast the industry's move from RTL to SystemC design in more detail, but it's clear to me that this is happening and that it has a lot in common with the gates-to-RTL transition. EDA vendors worked hard to ensure an easy path for their customers back then, and we're equally committed to evolving our tools and methodologies today for customer success. I'd love to hear from you about SystemC-based design. Are you doing it? Considering it? If not, why not? What can we do to help? I look forward to your comments.

Tom A.

The truth is out there...sometimes it's in a blog

If Only Carl Friedrich Gauss had IntelliGen in 1850

2011-08-18T15:00:00Z

The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in Wikipedia (http://en.wikipedia.org/wiki/Eight_queens_puzzle.) The challenge is to place N queens on an NxN chessboard in such a way that no pair of queens can attack each other. For those unfamiliar with chess rules, this means that no two queens can ever be found in the same column, row or diagonal.

Many mathematicians, including the mighty Carl Friedrich Gauss, have tried, and failed, to find algorithms to solve this challenge. Even today we do not know if the problem can be solved by an efficient algorithm (This is a so-called NP-hard problem in the Theory of Computation)

The solutions of N-queens are rare and irregularly placed in the hyperspace of possible placements. For instance, the case of 8 queens has 92 non-symmetric solutions out of more than 4 billion possible placements. So, the ability of a solver to solve N-queens demonstrates the effectiveness of its search mechanisms.

The Specman IntelliGen solving engine is based on what's called a finite-domain solver. This has many advantages over other BDD or SAT-based solvers used by our competition. Without getting too deep into details, there are some inherent problems of the BDD/SAT technologies that cause BDD solvers to explode for even small values of N (resources max out at N>=10) and SAT solvers suffer from poor performance (10X slower than IntelliGen for N=40 and simply does not finish for N=100). In contrast, solving a 100 Queens problem takes only seconds in IntelliGen using the following simple nested for each constraint solution:

<'
#define N 20;
extend sys {
    rows[N] : list of uint[0..N-1];
    keep for each (item_i) using index (i) in rows {
       for each (item_j) using index (j) in rows { 
          i<j => (item_i != item_j and abs(item_j-item_i) != j-i);
        };
    };
    
    run() is also {
        for each (pos) in rows {
            for i from 0 to N-1 {
                if (i==pos) { outf(" Q"); }
                else        { outf(" ."); };
            };
            out("");
        };
    };
};
'>

What are we doing in the above example? We have chosen to model the problem with a list of N integers in the range [0..N-1]. Each element represents a row. Each value is a column position of a queen in that row. So, the constraints used are:

No queens reside in the same column
- keep i<j => item_i != item_j
No two queens are ever on the same diagonal. Here we use the abs() built in e method to grab the absolute value of the difference between the column position of each queen.
- keep i<j => abs(item_j-item_i) != j-i)
It is sufficient to constraint only the cases i<j; otherwise we would double the constraints.

The run() method is just the pretty-printing. We go over all cells of the chessboard and print "Q" if the cell is occupied and "." otherwise. Here is an example of the printout:

Starting the test ...

Running the test ...

. . . . . . . . . . . . Q . . . . . . .

. Q . . . . . . . . . . . . . . . . . .

. . . Q . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . Q

. . . . . . . . . . . . . Q . . . . . .

. . . . . . . . . . Q . . . . . . . . .

Q . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . Q . . . . . . . .

. . . . . Q . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . Q . . . .

. . . . . . Q . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . Q .

. . . . . . . . . . . . . . Q . . . . .

. . . . . . . . Q . . . . . . . . . . .

. . . . . . . . . . . . . . . . . Q . .

. . . . Q . . . . . . . . . . . . . . .

. . . . . . . Q . . . . . . . . . . . .

. . . . . . . . . . . . . . . . Q . . .

. . Q . . . . . . . . . . . . . . . . .

. . . . . . . . . Q . . . . . . . . . .

No actual running requested.

Checking the test ...

Checking is complete - 0 DUT errors, 0 DUT warnings.

You might ask yourself, why is this important for verification? Well, the faster IntelliGen can solve a very challenging problem like N Queens, the faster it can solve the complex generation constraints of today's largest devices.

How fast is your constraint solving engine? Challenge your vendors' tools in this complex generation puzzle and post your results if you can.

Vitaly Lagoon

Vitaly Lagoon is an Architect working on the IntelliGen Generation Engine. Vitaly is a principal designer of IntelliGen's constraint solver and an expert on constraint solving techniques and tools. He is also a prolific researcher with more than 20 academic publications on constraint solving and program analysis in the leading international conferences and journals.

UCIS Coverage Standard -- Innovation Means Business

2011-08-17T21:00:00Z

Open solutions are just curiosities until the ecosystem figures out how to turn them into money. Java and Linux are good examples of that. When they first hit the "open" space, they were interesting technical solutions to interoperability (Java) and breaking the proprietary operating system monopoly (Linux). It's only when companies started wrapping products and services around them that they really electrified their respective ecosystems. The same thing is happening right now for the Accellera Unified Coverage Interoperability Standard (UCIS), an open and industry-standard API that promises to facilitate and improve on verification productivity.

As coverage is the language of verification, the openness of UCIS is the jumpstart that our ecosystem needs to enable new innovation and capabilities for one of the biggest challenge areas in Silicon Realization. UCIS is about bringing together suppliers, customers, and facilitators to solve some really difficult and challenging problems in the coverage interoperability space. For years now, customers have had the difficulty of trying to figure this out on their own -- writing their own scripts, maintaining their own libraries, devising their own databases, and developing their own translators to support some level of coverage interoperability.

Most industry initiatives are only partially balanced among suppliers, customers and facilitators. But the fact that the suppliers for all three of the major functional verification simulators are jointly and actively participating brings hope for those customers devising their own schemes, and brings new business opportunities for the entire ecosystem. Just like Java and Linux before it, the questions being asked draw facilitators -- those members of the ecosystem that provide value beyond the suppliers. We can expect to see offers of training, services, tools, and more in coming years -- which means that yes, UCIS Innovation Means Business.

This year, we will likely see a UCIS 1.0 standard released from Accellera. It's the first big step for coverage interoperability after literally years of working on it. We are already seeing customer, supplier and facilitator (see diagram, above right) participation increase significantly over the past 6 months. As a self-avowed UCIS proponent, I participate to help bring the ecosystem together and get more business flowing for everyone. If you would like to participate, there is lots more interesting work to do, and participation is highly encouraged. Simply join Accellera at http://www.accellera.org/home.

Metric Driven Verification Advocate & UCIS Proponent,

John Brennan

What I Learned Traveling Across the Silicon Prairie

2011-08-16T14:00:00Z

Inspired by Brian Fuller's cross-country "Drive for Innovation", last week I jumped at an opportunity to head out and visit customers in the heartland of America.

Here were the common themes heard during the trip:

(1) Discovering Power People Didn't Know They Already Have
A lot of people don't realize that support for the things they need to do are actually in our products already (in some cases, it's been there for years). However, because they are frozen on an older configuration, or the methodology to exploit a given set of features in a particular order isn't immediately obvious, they think they need to buy some other piece of software to get them where they want to go. It's a real win-win to be able to show them the power already at their fingertips.

(2) Formal & ABV really is going mainstream
Echoing my experience at DAC and other industry events over the past year, at both our Incisive Seminars and direct customer meetings Formal, ABV, and especially the mixed technology Assertion-Driven Simulation (ADS) were of high interest. To wit: people actually holstered their smartphones during the ADS segment of the seminar/presentation, and peppered me with questions about it. As per point (1) above, to the delight of several users they were pleasantly surprised they could go back to their desks and try ADS and some other techniques right away.

(3) EDA360 needs are clear & present
I had several people ask me about the EDA360 roadmap. Specifically, the gist of the conversation was an affirmation that the issues raised by the vision paper (apps-driven specs & monetization, IP integration vs. creation, etc.) were their day-to-day challenges. In short, they made it clear that the EDA360 initiative was right on the money and advised us [Cadence] not to drop the ball on executing to this strategy. These remarks came from end users at a very competitive account -- so it's clear that EDA360 principles are resonating with real, front-line users.

Do these notes square with your summer trip reports? Please share your experiences in the comments below, or contact me offline.

Happy Verifying!

Joe Hupcey III

On Twitter: @jhupcey, http://twitter.com/jhupcey

Verifying AMBA® 4 ACE Designs – Cadence is Ready to Help, Now

2011-08-16T01:00:00Z

ACE is here. Are you ready?

Designers of multimedia smartphones, tablets, and other mobile computing devices face greater challenges than ever. They have to deliver ever more capable and responsive systems, yet must also consume the least amount of power possible -- certainly no more than their competitors.To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need to squeeze the last drop of performance and power out of these compute clusters is now paramount. A big area of opportunity for performance gains/power reductions is through moving software-based cache-coherency management into hardware. ARM introduced the AMBA Coherency Extensions (ACE) protocol in June 2011 to address these very needs.

But alas, as we all know, there's no free lunch. Placing such an extensive additional function into hardware significantly expands the functional verification challenge and risk. Cadence recognized this well over a year before the ACE specification became public. In close collaboration with ARM we launched an aggessive development program to deliver a complete ACE verification solution in time for ARM's lead Cortex-A15 customers to use. That goal was accomplished and enabled Cadence to have mature verification IP (VIP) in time for ARM's public announcement of ACE.

More Info Available

The need for ACE and ACE verification as well as Cadence's VIP solution are discussed in the recently published EE Times article "Get control of ARM system cache coherency with ACE verification". I encourage you to take a look.

Get In Touch

And, as you plan your ACE or AMBA® 4 based system, I recommend that you connect with Cadence, the leading experts in this field. We have the most capable and mature solutions to help. Talk to you soon!

Pete Heller

The Return of the Son of Real-World Assertions

2011-08-01T20:00:00Z

I've received some nice feedback on my previous two posts about real-world situations that would benefit from assertions, so I will forge ahead with a few more examples. Last time I mentioned the DMV clerk who told me that glasses were required while driving if one eye was below the threshold but not if one eye was completely devoid of vision. One reason I remember that incident so clearly is that the clerk apparently failed to see any problems whatsoever with this line of reasoning.

That incident reminds of a trip last year when my family and I missed a connecting United Airlines flight because the first flight was running late. We ran to the gate and, of course, the plane was still there but the jet bridge door was closed. A bone-headed gate agent snippily informed me that we were being denied boarding because we had "not checked in at the gate" in time. I was dumbfounded. I pointed out that we were on another United flight and so of course we had not checked in at her gate. There were at least a half dozen of us trying to make the connection but she absolutely refused to re-open the door.

Of course, she knew perfectly well that we were all connecting and that the first flight was late. Her computer showed her that; airlines all the time wait a few minutes for connecting passengers from their own delayed flights. My guess is that the flight was oversold and that she had given away our seats despite knowing that we were arriving imminently. I could not believe that I was standing there listening to a presumably sentient human being scolding us for "not checking in" while we were on another flight on the same airline. She was missing an assertion for sure, and a lot more to boot.

In my last blog, I also talked about the closed financial services office directly customers a half-hour away "to serve you better." For another example of a mismatch between distance and convenience, type "cheap CDs" into your favorite search engine. I did this in an attempt to find some sites offering new or discounted music that I hadn't discovered yet. In the very first page of search results I saw a link for Princeton Record Exchange, and upon clicking it I was greeted with:

Can't Find It At
San Jose CD Stores?
Visit us in Princeton, New Jersey

That didn't surprise me; individual record stores all over the world sell on their own Web sites as well as through the usual channels (ebay, amazon, GEMM, etc.) But then I saw "We do not currently list our inventory or sell online" so I realized that when they say "visit" they really do mean a physical visit. So just for fun I clicked on "Directions" and requested a map for driving from San Jose to Princeton. I enjoy browsing at record stores, and this looks like a good one, but somehow I don't think I'm likely to drive 3,000 miles just to visit.

My final example for this post will be distressingly familiar. I had just finished an online purchase at some site or another when I was asked if I wanted to take an "online shopping cart survey." I don't remember which site I was using, but it was one that I frequented enough to be willing to give feedback. So I clicked on the link and up popped a page stating "This feature is currently not available." This is a good example of where an actual assertion would have helped: "if the survey is unavailable then don't ask the customer about it."

At least I didn't fill out a survey, try to submit it, and then see a failure. The latest (July 2011) edition of IEEE Computer magazine has a really good commentary on "Programmed Politeness" by Norwegian Professor Kai A. Olsen. He cites many such examples where programs and Web sites do things that defy common sense. The article is available from the IEEE but it looks as if you have to be a subscriber to access it. If you're not an IEEE member, here's an excuse to join. In the meantime I'll continue looking for more of my own examples of real-world assertions.

Tom A.

The truth is out there...sometimes it's in a blog.