Functional Verification

Built-in Message Logging – Part 1 of 2

2010-03-11T14:00:00Z

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK]

Messaging is important for two main reasons:

It is essential for debugging

It can greatly impact simulation performance

This is why Specman has a messaging infrastructure built-in to provide an easy to use, scalable and efficient mechanism. Furthermore, Specman’s messaging capabilities allow you to do almost anything which you can conceive with messaging: colouring, formatting, rejection, modification, redirection, etc.

The infrastructure uses a predefined unit called a message_logger to deal with message requests. Message requests are made using the message() action. By default, the “sys.logger” message logger is available, where sys.logger will deal with all message actions if you do not specify your own. However, you can and should instance your own message_loggers, where at a minimum I’d recommend each UVC in a testbench should have its own message_logger. In practice, it is very likely that major units like agents and monitors will also have their own message_loggers.

Given this background, here are some message_logger first principals:

When a message request is made, this message is "seen" by every message_logger from the unit containing the message action, through each direct ancestor, all the way up until it reaches sys.logger.

Each message_logger has associated with it a maximum of 2 destinations: the screen and a file.

Each of these loggers may have been configured differently, where some loggers may have been configured to ignore a given message. In the “ignore” case, message requests still get passed on up the chain to sys.logger, but only message_loggers which have been configured to respond to the message will do so; and only if that message request has not already been sent to the same destination by a message_logger closer to the origin of the message request. i.e. the same message request will not be sent to the screen by more than 1 message_logger.

Even if a message logger deals with a message request, it still passes that message request up the hierarchy. This is because that message_logger does not know if a message_logger further up the hierarchy is configured to send the same message to a different destination (for example, a file to which the message has not been sent by another message_logger).

What about the amount of messages and the level of detail required from them? In general, two factors come into play:

Clearly different levels of maturity of verification environment or RTL strongly influence the message quantity & quality. For example, it’s oftern helpful to have lots of detailed messaging early on in the environment bring up and debugging process, then thin it out as the environment matures so you don't have thousands of detailed messages in our logs potentially obscuring important activity.

Verification at different levels of abstraction also influences messaging. While similar in practice to (1) above, in this case as we move from module to system level verification then the messages from the lower level become less relevant. In fact, the system integrator probably does not have enough detailed knowledge of the low level block to make sense of the message anyway. That said, unearthing the roots of a system level bug may require a temporary reactivation of detailed messaging for a particular monitor instance connected to a particular DUT interface.

In the next installment of this series, I’ll share some tips on how to programmatically control message display to help speed your debug process.

Michael Avery
Cadence Services Organization, UK

VIP Portfolio Extension: New AMBA 4 Protocol Support

2010-03-09T00:30:00Z

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol. Here is the official announcement, which includes AMBA4 and VIP highlights.

What this means in practical terms:

If you have licenses for the Cadence VIP Portfolio (part number "VIP100"), you will receive the AMBA 4 VIP for no additional charge when it goes into production. If you are qualified and willing to be an Early Access user, you will receive it even sooner. To request early access, contact your friendly local AE or Salesperson (or email us an we'll forward the request).

Like all VIP in the Cadence VIP Portfolio, this OVM-compliant UVC has the Compliance Management System (CMS) built-in -- meaning the full set of AMBA4-specific sequences&scenarios, its coverage model, and detailed compliance checks and metrics -- all automagically tracked via a Compliance vPlan -- are all included.

FYI / brief history lesson: the AMBA UVC is easily one of the most popular, time-tested UVCs in the Portfolio. It's in use / has been used by 1,000s of projects, and the code base is one of the most mature pieces of VIP anywhere -- built on almost 10 years of AMBA VIP experience!

Happy verifying!

Team Specman

Have You Considered e Lately?

2010-03-05T14:00:00Z

Richard Goering's recent interview with Mitch Weaver on the future of Specman and e put me in a reflective mood about my own evolving opinions. My hands-on experience with Specman is minimal; back in my 0-In applications days I co-developed a joint demo with Verisity (prior to acquisition by Cadence) in which I had the chance to do a bit of e testbench coding. I was very familiar with formal at that point, but it was my first exposure to constrained-random simulation and I was impressed.

Six months later I was working at Synopsys, where I was deeply involved in their SystemVerilog rollout. My impression there, based largely on the fact that I talked almost exclusively to SystemVerilog and Vera users, was that e was dead or dying. Fast-forward a couple of years, and I joined Cadence. I can honestly say that nothing I have seen or learned in my time at Cadence has surprised me as much as finding out as soon as I joined just how powerful and popular e really is.

Mitch does not overstate reality at all - Specman and e continue in very broad usage with very few users switching to SystemVerilog and, in fact, new projects and new companies signing up every year. Of course, by now I've had the chance to talk to many e users and I understand how its technical advantages fuel their passion for the language. It's nothing against SystemVerilog to acknowledge that e has some unique features for advanced verification; it's a simple statement of fact.

However, I do talk to the occasional customer who is "e-lergic" (an old Verisity term) and who doesn't even want to hear e mentioned. Some are actually suspicious that our support for e somehow compromises our support for SystemVerilog! As Mitch explains in the interview, this is simply not the case. We support all IEEE-standard languages equally well, and enable just about any combination of e, SystemVerilog, and SystemC models in customer verification environments.

Since there are such strong opinions about e out there, I'm frankly surprised that there have been no comments on Richard's interview. I'll try for some response here since I'm quite curious to know what all you testbench developers really think. If you're unwilling to consider e, I'd like to know why. If you have an open mind on verification languages but didn't choose e, I'd like to know why. If you did choose e, I'd still like to know your reasons. So ... have you considered e lately?

Tom A.

The truth is out there...sometimes it's in a blog.

Why OOP Falls Short For Verification

2010-03-04T01:30:00Z

Last week at DVCon, frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs". In the following video, Matan elaborates on his paper, where it becomes clear that OOP languages like -- well, you know -- are at an inherent disadvantage vs. AOP approach (like in e) when it comes to the unique requirements of verification.

Click here if the embedded video doesn't play.

Joe Hupcey III for Team Specman

DVCon 2010 - Day 3

2010-03-02T14:00:00Z

Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3.

The images and notes include highlights from:

A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper

The paper "Tweak Free Reuse With OVM"

A paper on "Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCs"

The closing panel "Ever Onward! Minimizing Verification Time and Effort"

I also had the pleasure of interviewing one of our long time Verification Alliance partners, AMIQ, in their first appearence at DVCon (yes, they are growing even in these tough times!). In this video, their director of marketing Corina Mitu introduces their company, their "OVM aware" integrated device environment "DVT", and some new announcements ...

If video fails to launch click here.

Last but not least, my colleague Richard Goering has been writing detailed articles on the main keynote and panel sessions.

Enjoy!

Joe Hupcey III

DVCon 2010 Rocked!

2010-02-27T07:32:00Z

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010, and I have to say that it was a really good show. This is arguably the most important conference of the year for verification. DAC is lots bigger of course, but DVCon is really focused and there's a core group of colleagues and customers that always make it a fun and simulating event. Although DVCon is still officially the "Design & Verification Conference & Exhibition" every year it looks more and more as if the first ampersand is living on borrowed time.

Cadence and our customers had an especially active presence at DVCon this year, plus I always like to check out what our competitors and their customers are doing, so I couldn't possibly attend every session I wanted. I was really impressed with the technical papers that I did see, especially talks from Doulos on connecting SystemVerilog withC/C++/SystemC and on asynchronous assertions. They have a knack for presentating complex topics in a way that works even for those of us who no longer think about simulation timewheels on a daily basis.

The panels were generally lively, with some pithy comments that I (and others) tweeted in real time. I was really pleased with our sponsored lunch and its panel on debug. It was great that our CEO Lip-Bu Tan made his DVCon debut with a well-attended keynote address. Finally, I was just delighted with the pervasive OVM-related content -- our lunch, the UVM update at the Accellera lunch, exhibition floor demos, three tutorials, and at least five technical talks including the Best Paper award. It's only a day after the closing session and I'm already looking forward to next year!

Tom A.

The truth is out there...sometimes it's in a blog.

DVCon 2010 - Day 2

2010-02-26T14:45:00Z

Click here or on the image below to go to the annotated photo blog of DVCon Day 2.

Photos & notes include highlights from:

Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives"

Lunch panel on "OVM found the bugs, now how do we debug them faster"

Cadence CEO Lip-Bu Tan's keynote on "Breaking Through The Efficiency Barrier"

Industry Leaders panel on "What Keeps You Up At Night?"

Some shots of the show floor

Enjoy!

Joe Hupcey III

DVCon 2010 - Day 1

2010-02-24T15:00:00Z

Click here or on the image below to go to the photo blog of DVCon Day 1.

While I've added descriptive captions to the images, allow me to address the FAQ: "How was the traffic on show floor?". My unscientific observation was that the floor was a little lighter than last year, but this was a result of the tutorials being better attended and/or they "held" their audiences for longer.

Enjoy!

Joe Hupcey III

DVCon "Day 0" - Quick Report From SystemC Day

2010-02-23T04:32:00Z

If you were looking for more evidence that the transition from RTL to ESL is gaining momentum, today at "Day 0" of DVCon (a/k/a "SystemC Day") you would discover plenty of supporting data points. Here is a brief video interview with my colleague Steve Svoboda on the day's events, how far we've come from the first wave of SystemC hype back in 2000, and what Cadence is doing in this space:

If the video fails to launch click here.

Additionally, I had the pleasure of sitting in on the TLM 2.0 tutorial. While all 3 presenters -- John Aynsley of Doulos, Michael "Mac" McNamara of Cadence, and Michael Meredith of Forte -- had a great mix of detailed technical & high-level information. In particular, Mac's blunt declaration, "You can keep your head in the sand, or realize that today we need to move to higher abstraction for design and verification", was a bracing standout.

Mac outlines to the TLM 2.0 tutorial audience why the time for higher level abstraction is NOW.

Bottom-line: this "day 0" of events was a great warm-up for the rest of the show, and I'm looking forward to day 1!

Joe Hupcey III

Reference Links
The official DVCon site
http://www.dvcon.org/

Comprehensive list of Cadence-sponsored events & papers
(Be sure to sign up for our free lunch panel on the growing debug crisis on Wednesday)
http://www.cadence.com/mail/dvcon2010.html

Images from last year's show to give you an idea of what it's like, in case you have never been to a DVCon before.
http://www.flickr.com/photos/24605532@N08/collections/72157614716018724/

Editor For OVM Field Registration Macros

2010-02-22T23:20:00Z

The OVM SystemVerilog Class Library has built-in automation for many service routines that classes need for printing, copying, comparing and so on. OVM allows you to specify the automation needed for each field and to use a built-in, mature and consistent implementation of these routines. For each field you must use OVM field registration macros as in the example below:

...

rand bit [15:0] addr;

rand xbus_read_write_enum read_write;

rand int unsigned size;

rand bit [7:0] data[];

rand bit [3:0] wait_state[];

...

`ovm_object_utils_begin(xbus_transfer)

`ovm_field_int (addr, OVM_ALL_ON)

`ovm_field_enum (xbus_read_write_enum, read_write, OVM_ALL_ON)

`ovm_field_int (size, OVM_ALL_ON)

`ovm_field_array_int(data, OVM_ALL_ON)

`ovm_field_array_int(wait_state, OVM_ALL_ON)

...

Inside a single dedicated `ovm_*_utils_begin...end block, you must use dedicated macros for each field type. For example `ovm_field_int for a simple int or `ovm_field_aa_int_byte_unsigned for an associative array of integral types indexed by the byte unsigned.

If you are hesitant and your head aches when matching the right macro with the right type, the OVM Field Editor of the already well known DVT (Design and Verification Tools) Eclipse Plug-in IDE comes to rescue:

You can quickly check whether you have unregistered fields or registration errors. The DVT OVM Field Editor allows you to click on a field and register it with the right macro or customize it's printing, copying, packing and other controls. Based on the enclosing class type (object, component or sequence), the right `ovm_*_utils_begin...end< enclosing block for the registration macros is also created.

From now on, just declare your fields, then open the OVM Field Editor, select all fields and click Register. That's it!

Just don't forget to read more about the DVT Eclipse Plug-in and get your free trial license from www.dvteclipse.com.

=genIES

DVCon: Showcasing The Cadence Passion For Verification Excellence

2010-02-22T21:15:00Z

Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page. Highlighted below are two of the items that I think will be of special interest.

Tutorial: OVM Advanced Topics

With UVM based on OVM, this is a must see. We will start by describing the latest on OVM for multiple languages -- a requirement voiced by many users for UVM. The tutorial will then get into the guts of the OVM Low-power methodology, OVM for Assertion Based Verification, and OVM for Acceleration. If you are an OVM user today, this will show you what's coming. If you are a VMM user, it will show you what you'll be getting as you move to the UVM.

Panel: OVM Found the Bugs, Now How Do We Debug Them Faster?

As our technical team travels the world, we hear time and time again that debugging complex environments is becoming a huge challenge. This panel will dive into real-world debug challenges users face and we'll be debating the approaches and methodology to address them. Since this is really a state-of-the-art discussion, the panel will include representatives from Cadence, SpringSoft, the verification user community.

People Make DVCon Great

The biggest thing that makes DVCon so special is that it attracts the best people in our vibrant community. Our contribution this year includes a number of our lead technologists delivering papers and demos as well as the keynote address. See us in our booth, tutorials, papers, and panels or just stop us in the hall to talk. If there is one thing that binds us all it is the passion for verification excellence.

=Adam Sheriblog

Rev 2 of OVM e Scoreboard on OVMWorld.org Now

2010-02-18T22:30:00Z

Just in time for DVCon 2010, I'm happy to inform you that revision 2 of the OVM e Scoreboard was just uploaded to OVMWorld: http://www.ovmworld.org

The main changes from rev1:

A proper User Guide containing detailed descriptions and code examples for several popular use models
Performance improvements in the search algorithm

I encourage everyone who has already downloaded the original OVM e Scoreboard to download this new version (if only to get the new User Guide for reference). From mails we get, I know that several companies already have implemented a scoreboard using this infrastructure. Now, with the new examples and documentation, I am sure this task will become even easier.

As always any comments and questions are most welcome.

Happy verifying!

Efrat Shneydor
Cadence Methodology R&D
(and frequent Team Specman guest blogger; author of the hit series on Performance Aware e-Coding Guidelines)

Cadence Exec: Why Cadence is Comitted to e/Specman

2010-02-16T19:00:00Z

In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering.

As you'll see, with statements like, "Bottom line: cutting back on Specman/e would be like cutting our own throat", Mitch doesn't mince words about the depth of Cadence's commitment to our favorite platform.

Happy verifying!

Team Specman

OVM Community Contributions: Wildly Popular And Clearly Essential

2010-02-16T14:00:00Z

A couple of weeks ago, before going to bed one night I checked the statistics for the OVM World site. What I saw was really cool - exactly 10,000 registered users at the moment I looked! Being a social media guy these days, the first things I did was to tweet about it, and I was glad to see several re-tweets by OVM colleagues who also found this interesting and exciting.

My topic for today is another really cool thing I learned from the OVM World statistics: the OVM Community Contributions area is every bit as popular as the official OVM release kits. We introduced the Community Contributions area on OVM World about a year and a half ago as a way for anyone to contribute examples, ideas, suggestions for future OVM releases, etc.

We expected user interest, but I have to say that the response has exceeded my expectations. As I type this, the OVM World statistics tell me that there have been just over 24,000 downloads across all the contributions and just shy of 32,000 downloads across all versions of the OVM Kit. So the total contribution downloads are about 75% of the total kit downloads.

The first OVM kit was posted just over two years ago, and first contribution a year and half ago. So the the contributions area has been around roughly 75% of the time that kits have been available, leading to the conclusion that kits and contributions are essentially tied in terms of popularity. I must admit that I was a bit surprised (but delighted) by this result.

So what can we conclude? Clearly the Community Contributions area has played an essential role in the OVM ecosystem. No matter how quickly new features are added to official releases, users will come along with useful verification technology in between those releases. The contributions concept is a great way to keep the ecosystem dynamic and vital.

The statistics reinforce my stated position that I fully expect OVM World to continue even after the OVM has been standardized by Accellera as the UVM. Standards by their very nature do not get revised very frequently, so it will be essential for users to have a dynamic place for hot new verification technology that complements the UVM. OVM World will serve this need admirably.

Tom A.

The truth is out there...sometimes it's in a blog.

DVCon 2010 For The Specmaniac

2010-02-15T15:45:00Z

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored activities is posted here). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs. Hence, if you are going to the event, please consider printing out the following "DVCon 2010 Guide for the Specmaniac".

Monday February 22 - "SystemC & ESL day"

Granted, day 1 of the program is not really called "SystemC & ESL day"; and it's not even about Specman or the e language. However, it's clear that the trend of DUTs moving from RTL languages to higher abstraction with SystemC is starting to snowball (as at least 15-20% of Specmaniacs already know). Hence, depending on the degree to which your projects are aligned with this trend, Specmaniacs should attend either the North American SystemC Users' Group meeting on Monday morning, or the TLM 2.0 tutorial in the afternoon, or both. (Related FAQ: if ESL / TLM / SystemC is the wave of the future for design, is it the wave of the future for verification too? The paper being given by Cadence R&D Architect Matan Vax on Thursday morning (highlighted below) will address this question head on ...)

Tuesday February 23, 1:30pm-5:00pm, (Fir Ballroom):

Tutorial on OVM Advanced Applications
This techtorial will include updates on OVM e itself, as well as in the context of advanced applications like multi-language testbench integration, Verification IP (VIP) creation & integration, low power, and acceleration. Come prepared to take plenty of notes because the presenters will walk through many detailed code examples.

Tuesday Feb. 23 and Wednesday Feb 24, 2:00pm-6:30pm:

Specman technology in the Cadence booth (#505)
As always, Specman technology is directly or indirectly a cornerstone of the various demos -- OVM, Verification IP, metric-driven verification & Enterprise Manager updates, ESL & TLM updates, etc. The best part: at a relatively small show like DVCon, there is often the opportunity to digress from the primary demos and deep dive into specific Specman technology updates -- just ask us!

Additionally: our partner AMIQ has a booth at DVCon, where they will be showing new features in their DVT integrated development environment. To whet your appetite, here is a brief demo of rapid e coding with DVT, and some general background on the company itself.

Wednesday February 24, Session 4, Paper 4.2 at 11am, Oak room

Paper: "Apples Versus Apples HVL Comparison Finally Arrives"
Ever wondered how languages like e, SystemVerilog, and SystemC stack up for different applications and use cases in a straightforward, side-by-side comparison? If so, this is the paper you have been waiting for!

Wednesday February 24, Lunch Panel 12:30-1:45pm, Pine/Cedar room

OVM Found the Bugs, Now How Do We Debug Them Faster?
Clearly, streamlining the debug progress is of high importance to Specmaniacs, so please join us for this important panel discussion.

Note: the M.C. for the panel will be familiar to many Specmaniacs: Distinguished Engineer Mike Stellfox. Be sure to re-connect with Mike before or after the panel; or even better, during the panel fire off a question to him and/or one to vector to the panelists.

Wednesday February 24, 2:00 - 3:00pm, Oak/Fir room

Keynote Presentation: Breaking Through the Efficiency Barrier
As with the lunch panel, while this keynote by our CEO Lip-Bu Tan isn't directly about Specman (IMHO, a missed opportunity, but he *is* the boss ;-) the speech's focus on how companies can break through the efficiency barrier with higher abstractions of design and verification, reuse, metrics, and up-front tradeoffs is of obvious importance to anyone in D&V.

Thursday February 25, Session 7, Paper 7.1 at 8:30am, Siskiyou room

Paper: "Where OOP Falls Short of Verification Needs"
Presented by Cadence R&D Architect Matan Vax, the paper title says it all: at a certain point on the scalability curve, OOP-based languages start to break, given the unique requirements of verification itself -- vs. design-oriented applications like ESL or firmware development. To put a finer point on it: this paper will enable Specmaniacs to describe exactly why e is perfectly suited for massively scalable verification environments.

FYI, if you are into the nuances of languages in general, be sure to chat with Matan since he is a walking Rosetta Stone of D&V languages.

Thursday February 25, Session 7, Paper 9.3 at 10:30am, Cascade room

Paper: "Tweak-Free Reuse Using OVM"
While bits of this paper will be old news for long time eRM, er, OVM e users, Solutions Architect Sharon Rosenberg (another familiar face to many Specmaniacs!) will cover a lot of new ground and emerging best practices he is seeing at the many customers he's called on in the past year.

Last but not least:
It bears repeating that verification gurus like R&D Architect Matan Vax, Distinguished Engineer Mike Stellfox, Solutions Architect Sharon Rosenberg, and many others will be at DVCon to hear your latest verification-specific concerns and challenges. If you don't run in to them in the conference halls, just ask any Cadence person help locate them.

We look forward to seeing you next week!

Team Specman

Reference links
The official DVCon site
http://www.dvcon.org/

Comprehensive list of Cadence-sponsored events & papers
http://www.cadence.com/mail/dvcon2010.html

Images from last year's show to give you an idea of what it's like, in case you have never been to a DVCon before.
http://www.flickr.com/photos/24605532@N08/collections/72157614716018724/