Online Support, http://support.cadence.com, provides access to support resources including an
extensive knowledge base, access to software updates for Cadence products, and
the ability to interact with Cadence Customer Support.
In the June release
of Cadence Online Support, many new features and functionalities were added to
help users filter and narrow their search results, to provide feedback opportunity
via Foresee Survey, and to provide additional browser support. Now the site
supports all IE 7x-10x, Mozilla Firefox, Google Chrome, and and Safari Browsers.
The testing for the next release with more new features and enhancements
is continuing while I am writing this blog. While I was enjoying all these released
new features, as a verification engineer, I also was interested in finding out good
knowledge documents that were shared on the site, and if I could easily find
them. And indeed, I could easily find many application notes, RAKs, videos, and articles released in last quarter, along with site release updates,
that are very helpful. You can download your copies from http://support.cadence.com now and check out for yourself. Please note that you will need
customer credentials to log on to the Cadence Online Support website.
utrace to Debug SystemVerilog Randomization Problems: The constrained
random verification environments can exhibit the following problems:
- Expected values are not reached
- Certain values are chosen less frequently
or more frequently than expected
- The constraint solver calls take too long
- The solver is unable to find a solution
for a given constraint set
- The solver is unable to find a solution
with certain starting conditions including variables that are not random or
handles and arrays that are not initialized
- The solver runs out of memory
The app note "Using utrace to Debug
SystemVerilog Randomization Problems" describes the utrace debugger
feature of the SystemVerilog constraint solver, which can be used to
identify and debug problems in a SystemVerilog-constrained randomization
Article 20257945: "How to compile multiple libraries with a single invocation
of ncvlog/ncvhdl or irun"
In many environments, it can
be useful to compile HDL source code into more than one library. Often this is
done by means of multiple invocations of the ncvlog or ncvhdl binary. Read this article to learn how.
Annotation with Minimum, Typical, and Maximum Delays: This short 8-minute
video describes how IOPATH and INTERCONNECT delays are annotated, how MIN,
TYP, and MAX delays are implemented, and how annotation is analyzed in the
You can also find the related Troubleshooting
Article 20264486: "How to annotate maximum delay for one
instance and minimum delay for other instance."
Library Installation and Setup: This video provides a step-by-step walk
through of downloading and installing the UVM-ML OA library from the Accellera
forum page. This is followed by details on where to find the
documentation, and how to run one of the examples delivered with
Article 20257843: "Understanding SystemVerilog Random Stability"
Random stability can be
defined as the resistance of random results to code changes. A key requirement
of verification is the ability to recreate the exact conditions that found the
problem so that the fix can be verified. When random stimulus is used in a test
environment, in order to allow debug-fix-debug cycle, it is required that the
same random numbers are generated when the same test is run multiple times.
This should hold true even when a change (fix) is added to the code in either
the DUT or test bench. This concept is called random stability.
This article describes the concept of and how
to achieve random stability in any verification environment involving
SystemVerilog constrained randomization.
Article 20266731: "How to get switching information (ON/OFF)
about power domains during simulation?"
Users often require
switching information about the all or selected power domains in low-power simulation. They want to get the simulation time whenever a power domain is
switched ON or OFF. This information is quite useful, while creating complex
system-level testcases for power simulations. This article describes couple of
ways for achieving this functionality in the tool.
7. All you ever wanted to know about the vManager Server
Methodology and Server Setup is now available on Cadence Online Support.
The server setup section describes the operations that can
be done on the servers, while the server methodology section answers
questions on the methodology to use the servers.
Server Methodology: This collateral describes Postgres and vManager server states,
operation summary, server statuses, recommended server topology, data storage
detail, software install and migration, current remote capabilities, and PG DB
Server Set-Up: This collateral describes the vManager server setup in a detailed
manner to equip users with a better understanding of the setup: environment
variables, topology and terminologies, and various operations. It also enables
users to collect and debug problems encountered while starting and accessing SQL
Article 20250009: "How to turn off concurrent assertions while leaving the
inline assertions on?"
engineers often require switching information about the all or selected power domains
in Low Power Simulation. They want to get the simulation time whenever a power
domain is switched ON or OFF. This information is quite useful, while creating
complex system-level testcases for power simulations. This article describes a couple of ways for achieving this
functionality via Cadence Incisive Enterprise Simulator.
Article 20257827: "How to reduce time to create vcd for power analysis?"
Conventionally, a directed test is created for power analysis. To activate most of the logic at same time, a
switching activity file is extracted in any of following formats: vcd, tcf,
The Cadence Encounter
Power System (EPS) reads activity file for power estimation. It is cumbersome to
include all scenarios in a single test to attain maximum activity and it takes
time to create such test and execute. The SHM to VCD conversion for lengthy
test also takes a long time, before power analysis can be started. This article,
thus describes how to reduce time to do power analysis for complex and huge
Article 20253114: "Isolation not placed due to driver filtering <D> in
CPF-based low-power simulation"
This article suggests what
are the various reasons of implicit isolation not being inserted due to driver
filtering during CPF-based low-power simulation? How to debug and fix? It also
points to another wonderful troubleshooting for a warning ncelab: *W,PRTNCON—Isolation Cell not placed on port.
Hmmm... let me leave with
bonus of two more troubleshooting tips, however, I will just provide title and
link, and will not describe them in brief. Please go and figure out for
Article 20266723: "Reinvoke
fails when run in an LSF environment"
Article 20267817: "How to extract a list of probed signals in either an interactive or post-process flow?"