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e and SystemVerilog: The Ultimate Race

Comments(0)Filed under: SystemVerilog, IES, e, IEEE 1647, Funcional Verification, Adam Sherer, UVM ML, IEEE 1800, simulation performance

For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language to the other. This makes a direct performance comparison difficult to measure. Until now.  

On April 21, 2014, SystemVerilog and e toed the line for the first direct SoC race. They were set-up in a long-pole test to allow each language sufficient run-time to establish the test as credible. As you can see at below, e started very strong and got out to an early lead. A moment later, SystemVerilog surged to the lead as shown in the next screen capture. This exchange continued relentlessly from Hopkinton deep into the Newton Hills. As the race continued it was just obvious: e and SystemVerilog are joined at the hip and this is a multi-language race. The only way to finish this race was to have the two languages work together. Turning onto Boylston St. and charging across the line, e and SystemVerilog finished the SoC (Sherilog on Course) together.

As much fun as this blog was to write, it was more important to take part in this race.  I am proud to have helped make a statement along with nearly 32,000 others in my 9th Boston Marathon.  I was also able to raise more than $5000 with my patient-partner Linda as I ran for the Boston Children's Hospital.

=Adam Sherilog 

PS: If you are interested, you can donate to our Children's Hospital Team through the end of May. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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