Home > Community > Blogs > Functional Verification > incisive simulation and verification top 10 new things i learned while browsing cadence online support q1 2014
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing Cadence Online Support in Q1 2014

Comments(0)Filed under: SystemC, Specman, IES-XL, uvm, LSF, RAK, x-propagation, LPS, State Retention, vMananger, incisive simulation, Low Power Simulation, IMC, drm, Glitches

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and technologies.  

In this second quarterly blog, let me explain the "Once Resolved, Reused Forever" internal process for documenting knowledge on http://support.cadence.com/. It ensures that we are not solving a problem that has already been solved, and that we benefit from the collective experience of the organization and our customers. Yes, you heard it right. Our customers can also help enrich our knowledge database to help others. And, in fact, we encourage our users to use "Troubleshooting -> Submit Solution" from http://support.cadence.com/ Home Page menu.

Our knowledge team reviews and publishes, and circles back with the contributor.

The "Reuse-Improve-Create" knowledge process is an integral part of Cadence Technical Support. The process ensures that we have the most effective knowledge transfer among our own engineers and customers.

In Q1 2014, the teams across the Cadence Incisive Verification Platform developed the following collateral to support verification and design engineers in becoming well versed with Cadence verification tools, technologies, and solutions.

Download your copies from http://support.cadence.com/ now and check them out for yourself. Please note that you will need your Cadence customer credentials to log on to the Cadence Online Support http://support.cadence.com/ website.


1. One can get separate runtime profiler reports with basic or advanced profiler with the simulation profile options.

Article # 20236067: How to dump separate runtime profiler reports with basic or advanced profiler?


2. Sometimes there are situations where glitches on signals result in repeated re-triggering of the blocks which reference them. A Verilog always block executes when an object in the event control expression for the block has changed value from when the block was last executed. This default wait mechanism is sensitive to zero-width glitches on the variables that the block is waiting on. These glitches are usually created when a writer process assigns a default value to the variable and then overwrites it with a different value. Even if the writer changes the variable back to the old value, the zero-time glitch is sufficient to wake up the waiting block. When such glitches are combined with a combinational loop in the design, they can stall the simulation.

Article # 11594558: Using the -delay_trigger switch to avoid repeated retriggering of always blocks due to glitches


3. In low-power simulation, switchable domains in the design can be powered off, putting the domain into an unknown (X) state. If proper attention is not given to the design state before and after switching the domains, it can lead to an X-propagation issue in the design. Proper retention is needed to save states before the domain so that the states can be successfully written back into the sequential elements when the domain is switched on.

Article 20187515: State Retention: Examples to demonstrate usage of state retention in Low Power Simulation


4. In SoC designs many flip-flops exist without set/reset because non-resetable flip-flops are smaller and, therefore, save silicon cost. However, if such flip-flops are not initialized, then they become a potential source of X-propagation issues during simulation.

The requirements can be to correct the design to include set/reset for such flip-flops, or to initialize such flip-flops to avoid X-propagation in simulation. Please read the following article to get the answers.

Article #20187534: How to find Non-resetable Flip Flops in design and initialize them to avoid X-propagation in simulation


5. Many teams have C models of the algorithms or systems that they are developing. Integrating these C models into the SystemVerilog verification environment reuses these models. It allows fast stimulus generation and checking. It also allows the internal state of the C model to be checked if a mismatch occurs.

A set of guidelines and an example that demonstrates how SystemC models (or C/C++ models wrapped in SystemC) can be integrated within a SystemVerilog or UVM verification environment are available as a Rapid Adoption Kit (RAK). This RAK also demonstrates how models can be integrated for checking as part of a scoreboard and how they can be integrated to drive the simulation for firmware or software testing.

Rapid Adoption Kits


Application Note(s)

RAK Database

Integrating C, C++, SystemC Models with SystemVerilog and UVM



Download (0.8 MB)


6. The vManager server setup includes environment variables, topology and terminologies, and various operations. The document describes how to migrate quickly to a new build or a version. It also helps users in collecting information, and debugging the problems encountered while starting and accessing SQL database.   

vManager Sever SetUp - Introduction, Topology, Operations and Debug Techniques


7. Here are 5 videos for some common features/flow in Incisive Metrics Center (IMC).

1.      IMC Basic (Video)

2.      IMC Detailed Analysis (Video)

3.      IMC Reporting (Video)

4.      IMC Refinement (Video)

5.      IMC Refinement Resilient - IES 12.2 vs. 13.2 (Video)


8. Expression coverage is an important metric for code coverage that is widely deployed to measure how much of verification is completed or progress on coverage closure, yet it is not well understood. It has a wide variety of modes and switches to tune both performance and optimize on runtime to achieve coverage closure results. Also, the number of testcases required for good expression coverage closure could be optimized using this metric.

The Understanding Incisive Expression Coverage enables users to deploy expression coverage more effectively, and achieve faster coverage closure with optimal performance.

This is an overview of Incisive expression coverage technology and methodology that provides a basic understanding of the subject with opportunities for trade-offs that can be used while deploying this form of coverage. Doing so can help achieve faster coverage closure if the right settings are selected.

The tutorial includes a two-part video series explaining various Incisive expression coverage scoring modes, how to deploy expression coverage more effectively, and how to achieve faster coverage closure with optimal performance.


9. The application note "Verification Management DRM Setup and Configuration" describes how to configure the Distributed Resource Management (DRM) setting with the Incisive Enterprise Manager (EMGR) and Incisive vManager (VMGR) products. The document provides basic steps towards integrating EMGR with one of the predefined DRMs. In addition, it also details how to debug common configuration issues.


10. The verification of a design may require multiple technologies, languages, and products to work together. When the design itself includes Verilog, System-Verilog, VHDL, and SystemC, it is a mixed-language environment.  Specman can work with such designs.

In this AppNote "Controlling Specman Agents and Adapters in a Mixed-HDL Environment ", Avi Farjoun, Cadence Staff Support Applications Engineer, discusses how to successfully integrate all those languages into a single verification environment.  

Let me end with two bonus collateral references, one to a critical article and one to a verification IP applications note:

11. Article # 20227162: How to infer implicit Isolation on loads in VHDL generate block?

12. The application note, Integrating Cadence USB 2.0 Verification IP over DpDm Interface, explains how to create, configure, and instantiate Cadence USB 2.0 Verification IP in the testbench. It focuses on "Why do we need Dp/Dm translator?"


We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies. If you are signed up for e-mail notifications, you'll see the new solutions, app notes, videos, manuals, etc. as we post them.

Happy Verifying!

Sumeet Aggarwal 


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.