If you're an avid reader of Cadence press releases (and what self-respecting verification engineer isn't?), you will have noticed in our Incisive 13.2 platform announcement back on January 13th that Incisive Formal technology, with our new Trident cooperating multi-core engine, took top billing. But you would have needed to be very diligent to have followed the link in the press release to the Top 10 Ways to Automate Verification document that explained some other aspects of the Incisive 13.2 Platform. There, weighing in at number 6, was a short description of our latest verification app, for register map validation. Verification apps apply combinations of formal, simulation and metric-driven technologies to mainstream verification problems. This approach puts the focus on the verification problem to be solved, rather than the attributes of the technology used to solve it. The Incisive verification apps approach is defined by the following principles:
- Supplement a well-documented methodology with dedicated tool capabilities focused on a high-value solution to a specific verification problem
- Use the appropriate combination of formal, simulation, and metric-driven technologies, aimed at solving the given problem with the highest efficiency
- Provide significant automation for creating the properties necessary to solve the given problem, reducing the need for deep formal expertise
- Provide customized debug capabilities specific to the given problem, saving considerable time and effort
Verification App for Register Map Validation
The new Register Map Validation app generates properties automatically from an IP-XACT register specification. You can exhaustively check a multitude of common register use cases like value after reset, register access policies (RW, RO, WO), and write-read sequences with front-door and back-door access. All these sequences are shown in clear, easy-to-use debug views. Correct register map access and absence of corruption is difficult and time-consuming to check sufficiently in simulation.
The result is a reduction of verification set-up times and, combined with the Trident engine we mentioned before, huge reduction in execution times, reducing register map validation from weeks to days or even hours. But don't take my word for it - come to DVCon next week and hear Abdul Elaydi of Marvell, who will be presenting "Leveraging Formal to Verify SoC Register Map", and Rajesh Kedia of TI, who will be presenting "Accelerated, High-Quality SoC Memory Map Verification Using Formal Techniques", both on Wednesday, March 5.