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That Cowbell Must be Registered – Introducing the UVM SystemVerilog Register Layer Basics Video Series

Comments(0)Filed under: Functional Verification, SystemVerilog, verification, Incisive, universal verification methodology, Axel Scherer, UVC, Cadence, cowbell, IEEE 1800, UVM_REG, video series, Register Layer

In May of 2012 we launched the initial cowbell YouTube video series on the basics of UVM for SystemVerilog IEEE 1800 and e IEEE 1647.

This was followed by a video series on debugging with SimVision.

Then, we struck a different kind of cowbell by releasing a MOOCs course for Functional Verification on Udacity.

Now it is definitely time for more cowbells.

One aspect that was not covered in the UVM Basics series was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer.


The new video series is broken up into twelve clips:

  1. Introduction
  2. Testbench Integration
  3. Adapter
  4. Predictor & Auto Predict
  5. Register Model & Generation
  6. IP-XACT
  7. Register Model Classes
  8. Register API & Sequences
  9. Access Policies
  10. Frontdoor & Backdoor
  11. Predefined Sequences
  12. Demonstration

Go ahead and register your cowbells!

Axel Scherer

Incisive Product Expert Team
Twitter, @axelscherer


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