Home > Community > Blogs > Functional Verification > how to keep learning about advanced verification at your desk
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

How Can You Continue Learning About Advanced Verification at Your Desk?

Comments(0)Filed under: SystemVerilog, metric driven verification (MDV), ABV, methodology, metric-driven verification, connectivity, metric driven verification, metric-driven, : Functional Verification, advanced verification, e-language, Incremental Elaboration, RAK

How much time do you spend "playing" and "learning" before you try a new EDA tool, feature, or flow?
Do you really take a training class and sift through the documentation or books about the subject before you start project work? Or are you the type who has the knack of figuring things out on your own by taking a deep dive, head first?

Learning is an iterative and repetitive process.  Human beings spend most of their lives learning through a structured learning program in their school years, then an expensive and elective college adventure, leading to years of learning during their professional lives.  The big challenge that I have faced with learning is how to find the right learning vehicle that helps me discover what I didn't already know in a short period of time.   If you struggle with this aspect, you should look at Cadence Rapid Adoption Kits (or, RAKs).

Rapid Adoption Kits from Cadence help engineers learn foundational aspects of Cadence tools and design and verification methodologies using a "DIY" approach.   Don't get me wrong, instructor-led, structured training programs work beautifully if you can invest the time and money. But there is always demand for learning something simply and quickly in some corner of the world. 

Today, we have made available eight RAKs focused to help our users learn various aspects of digital IP and SoC functional verification methodologies and tools.

The RAKs provide an introduction to state-of-the-art verification solutions including Universal Verification Methodology (UVM), based on the industry-standard UVM Reference Flow donated by Cadence for digital and mixed-signal verification using Incisive Enterprise Simulator and Metric Driven Verification methodology (MDV). For implementation, the flow uses Incisive Enterprise Manager, as well as SoC verification techniques such as I/O connectivity using Incisive Enterprise Verifier and optimization of simullation performance  for large SoCs.

The examples referenced in the Rapid Adoption Kit exercises are based on the Cadence SoC Verification Kit.  You can view presentations, app notes, videos and/or download the package that also contains lab exercises, relevant scripts and instructions.

Download your RAK today at http://support.cadence.com/raks.

Happy Learning!

Umer Yousafzai

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.