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Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

Comments(0)Filed under: Functional Verification, SystemVerilog, metric driven verification (MDV), IES, Incisive Enterprise Simulator (IES), Aspect Oriented Programming, DVcon, IES-XL, debug, Mixed Signal Verification, AVS, Debug Performance, Specman/e, Incisive Debug Analyzer, debug tutorial

TUTORIAL: Fast Track Your UVM Debug Productivity with Simulation and Acceleration

Session: 5T on Thursday, Feb. 28th from 8:30AM - 12:00PM

For more details on the debug tutorial, click here

This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most efficient debug tools available. Class based software-oriented environments are best debugged using interactive debug techniques where the user has a much broader range of tools at their disposal. Traditional post process debug techniques can be valuable -- however, many limitations such as performance, and the lack of interactive features such as source level stepping, make debugging difficult. To be more efficient in post-process debug, these restrictions must be removed. The debug techniques presented in this tutorial will provide design and verification engineers with the latest techniques and tools available in the debug space, including a new novel solution that combines the best features of both interactive and post process debug.

Novel debug methodologies that will be discussed in this tutorial will allow users to:

  • Explore their test environment for static and dynamic information
  • Step forward or backward through the simulation, or jump to a specific point in the simulation
  • Investigate possible reasons why the simulation has reached a particular state through advanced go-to-cause features
  • Filter all messages coming from any platform (HVL and HDL code) and explore the cause of the messages

Additional topics to be covered in the tutorial are:

  • Advantages of interactive debug over traditional post-process debug
  • Preparing UVM environments for hardware acceleration
  • Advanced post-process debug techniques improving debug productivity by 40 - 50%
  • Unique advantages of class-based aware debug technologies 
  • Application of debug techniques to both simulation and acceleration engines, including assertions and coverage driven verification 

We will also explain how new data access to coverage and assertions in acceleration extend these methods to catch bugs unique to system verification. In short, we will provide design and verification engineers with the latest techniques and tools available in the debug space, including solutions combining the best features of both interactive and post process debug using both simulation and acceleration engines. 

So, if Debug is a big bottleneck in your overall verification effort, do not miss this debug tutorial on Thursday, February 28th at 8:30AM in the Donner Ballroom.

Looking forward to seeing you all at DVCon!

Kishore Karnane

 

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