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Event Report: Club Formal San Jose – Features and Techniques for Experts, Verification Apps for All

Comments(0)Filed under: Functional Verification, Formal Analysis, Incisive, ABV, IEV, IFV, assertions, formal verification, Chris Komar, assertion-based verification, Club Formal, Oski, apps, formal apps, Vigyan Singhal, Incisive Formal Verifier, Incisive Enterprise Verifier, bypass logic verification, Team Verify, Chelsio, liveness

Last week over 35 power users from over a dozen companies came together for the latest installment of "Club Formal" -- a user group meeting exclusively focused on topics in formal analysis and Assertion-Based Verification (ABV).  This instance of Club Formal featured several papers from Silicon Valley power users on expert-level techniques, as well as highlights of new "verification apps" that are highly automated such that any engineer can run them.  In addition to networking with industry peers, Cadence R&D and field specialists were on hand to share our product roadmap and discuss new requirements from the attendees to better align our R&D development with their needs.

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Here are some specific highlights of the event:

Expert Presentation
: Liveness vs. Safety
B. A. Krishna of Chelsio Communications Inc. treated the attendees to an encore presentation of his HVC-2011 paper, "Liveness vs. Safety - a practical viewpoint" (full citation below).   The DUT at the heart of the paper was a Deficit Weighted Round Robin (DWRR) arbiter, and the critical verification task was to check if the port will be eventually given access to a given grant, regardless of the weight distribution across ports. One verification option is to write this as a "liveness" property.  As Krishna explained, on the plus side this is easy and/or intuitive to write. However, for verification purposes it required considerable effort to identify abstractions that could get conclusive results for the property. 

The other option is to write a "safety property".  Unfortunately, this requires a lot of effort in finding out the upper bound for forward progress. This was a painstaking process, but once they had written the property, verification did not require any abstractions - it's practically DUT independent.  For the given project they had the opportunity to apply both methodologies and compare the two, and thus the conclusion of the paper was an insightful review of their results and/or which approach would make more sense in a particular scenario.   Given the amount of questions and discussion this paper prompted, it was clear the merits of both approaches were of keen interest to the audience.


Expert Presentation: Bypass Logic Verification
Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs.   If you miss a bug in the bypass logic the whole system can simply freeze.  In this presentation, Club Formal alumni and favorite speaker Vigyan Singhal of Oski Technology gave an encore of the 2012 DAC User Track Best Presentation award-winning paper on this challenging topic, entitled "Deploying Model Checking for Bypass Verification" by engineers from Cisco and Oski Technology (full citation below). 

For starters, the DUT was a bear featuring a tough-to-verify, 25-deep bypass logic schema.  In a nutshell, their technique was to use the DUT itself as a reference model based on the fundamental principal of bypass logic: whether the bypass is active or not, the results should be the same regardless. In this case, the input commands to the reference model (1st DUT instance) have been separated by 25 cycles where the bypass logic is inactive. However, the challenging twist is that input commands to the 2nd DUT instance are randomly separated by anywhere from 1 to 24 cycles.  Another key factor to their success was using "memory random" as a simple abstraction of the design depth.  This allowed the tool to concentrate on the key elements of the DUT/state space. 

Bottom-line: they achieved phenomenal results, with 10 bugs found in this already heavily simulated IP.   Indeed, many corner cases they reached with formal would have been practically impossible to reach with only a constrained-random, simulation-based testbench given the permutation of command-combinations, the number of cycles that each command pair was spaced out, and so forth.

Roadmaps and New Product Previews
Chris Komar of Cadence R&D - specifically, a leader of the Product Expert Team - took the stage to give sneak previews of a new verification app coming out in just a few weeks, as well as the 18 month roadmap for our whole verification apps portfolio, expert level flows, and enhancements to the Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV) platforms.

Allow me to again thank the attendees for their warm reception of our product roadmap, and being generous with comments about where you'd like to see more attention.  This feedback is invaluable to R&D, and as you saw we were all taking careful notes.

Lunch, Snacks and Networking!
Last but not least, the intermissions and social segments were of high value as well.   Whether it was the casual lunchtime discussions, or informal Q&A during the breaks, truly these venues - comfortable, community settings where users get to swap stories with other users to brainstorm solutions and share tips&tricks -- were some of the best parts of the day.  I know my Cadence colleagues appreciated your feedback and ideas!

Bottom-line:
An engaging, informative time was had by all, and I believe I speak for everyone in looking forward to the next Club Formal!

Until the next time, happy verifying!

Joe Hupcey III
for Team Verify

On Twitter: http://twitter.com/teamverify, @teamverify

And on Facebook:
http://www.facebook.com/pages/Team-Verify/298008410248534

Reference Info: Paper Citations
Haifa Verification Conference 2011: "Liveness vs Safety - a practical viewpoint"
B. A. Krishna, Chelsio Communications Inc, San Jose, CA
Jonathan Michelson, Cisco Systems, San Jose, CA
Vigyan Singhal, Oski Technology, San Jose, CA
Alok Jain, Cadence Design Systems, Noida, India

DAC 2012 User Track: 8U.2 - Deploying Model Checking for Bypass Verification
Prashant Aggarwal - Oski Technology, Inc., Gurgaon, India
Michelle Liu - Cisco Systems, Inc., San Jose, CA
Wanli Wu - Cisco Systems, Inc., San Jose, CA
Vigyan Singhal - Oski Technology, Inc., Mountain View, CA


P.S. Team Verify is working on the 2013 event calendar now.   Hence, this the perfect time to let us know If you would like to see a Club Formal in your area!  Simply jump to the Team Verify home page and "send Team Verify a private message".

P.S.S.  In case you are unable to attend a Club Formal near you, be sure to check out our calendar and archived recordings of free, technical webinars:
http://www.cadence.com/cadence/events/pages/default.aspx

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