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UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Comments(0)Filed under: Functional Verification, OVM, SystemVerilog, IES, multi-language, SystemC, e, IEEE 1647, IES-XL, accellera, uvm, webinar, UVM ML, IEEE 1800, UVM-ML, multi-language UVM

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e, SystemVerilog, SystemC, and C/C++ into one simulation is basic but insufficient for SoC verification.  The question asked by SoC verification teams is "how can these work together in a cohesive environment?"

Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. That work was first contributed to the now offline OVMWorld in 2009. It was updated to align with the Accellera Systems Initiative UVM standard and contributed to the UVMWorld in 2010.  Since then, this solution was updated several times to remain synchronized with the UVM and add new functionality. With more than 1,500 downloads, it remains the first and leading open-source solution for UVM multi-language applications.

On Thursday October 25 at 9:00 am PDT, we'll review the solution and discuss the latest new features.  This technical discussion will be lead by Gabi Leshem, Solutions Architect, and Guy Mosenson, Senior Solutions Architect using the Incisive Verification Kit delivered with the Incisive Enterprise Simulator.  The Incisive Verification Kit is a superset of the Cadence UVM reference flow (with 4,000+ downloads covering v1.0 and v1.1) available on UVMWorld.  During the discussion you will learn about the following topics:

  • Requirements for modeling multi-language UVM-based environments
  • How to implement and integrate a UVM-ML verification environment
  • Multi-language communication and synchronization features
  • Advanced debug techniques key to analyzing multi-language environments and resolving multi-language issues 

So if you are a verification engineer, designer, or manager interested in leveraging existing VIP and improving reuse, this webinar is for you.  You can register for the webinar here:  http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home.


 Adam "ML" Sherilog, Incisive Product Marketing Director 


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