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What Does it Take to Migrate from e to UVMe?

Comments(0)Filed under: SystemVerilog, Incisive Enterprise Simulator (IES), Specman, IEEE 1647, Aspect Oriented Programming, AOP, vr_ad, sequences, team specman, uvm, e language, constraints, scoreboard, UVM e, UVC, SCE-MI, UVM-e, advanced verification, Specman/e, Shneydor

So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e?"

Well, this is a bit of a trick question. The short answer is that if you've adopted eRM in the past, migration to UVM e will only take a few minutes. If your environment is not eRM-compliant, it will take you longer.

And now to the details. What exactly is UVM e, in comparison to native e (IEEE 1647), and to eRM? What is in UVM? And what's all the fuss about?

Let's start with a high-level view of the methodology. The UVM describes the creation of a reusable universal verification component (UVC). Each UVC defines a reusable verification environment for one protocol (AXI, PCIe, etc.) or a system (an interconnect, a bridge, etc.). The UVCs are built of agents, sequence drivers (sequencer), monitors, etc. Sounds familiar? Of course. This is eRM, and UVM is based on eRM.

So, the concept and methodology are the same. No "migration" required here.

Let's take a look at the technical details. Other than documentation, what utilities and infrastructure does the UVM package contain? UVM provides a messaging mechanism, synchronization between components, infrastructure for sequences definition and driving. Again, this should be no big news to any e user. These are things you learned in basic e training. It might seem like some terminology is not aligned. But let's look more closely. In UVM documentation or discussions you might have heard the terms "UVC," "sequencer," and "report." These are simply the UVM SV names for "eVC," "sequence driver," and "message,"; all terms you should be familiar with.

And this is why "What would it take to migrate from e to UVM e?" is a trick question. If you took Specman basic training and adopted its guidelines, you are already using UVM e. The "bread and butter" of UVM e has been part of e LRM (and Specman) for several years now.

To paraphrase the French playwright Molière, "Good heavens! For 10 years you have been using UVM without knowing it!"

So if you were simply concerned about trying out UVM, well, you already are using it!

But  Cadence has more to offer. UVM e is being extended with features and methodology examples that target system verification challenges. These new capabilities are part of Cadence UVM open source, which contains the following:

  • Base Types - The UVM base types define the components role in the environment, and can be used by other tools (also tools developed by users). For example, to perform some action on all units deriving from uvm_monitor. This is the only element in UVM e that requires modification of existing code, and is not a must in order for the environment to be UVM-compliant.
  • Testflow-run-time phases - Breaks run time into various phases, allows defining domains (with or without synchronization), re-runs to a specific phase and also skips to a future phase. (Note: There is ongoing work in the standards committee to implement this in SystemVerilog, but it is ready within UVM e.)
  • UVM Scoreboard - Infrastructure for data check, with searching and data transformation algorithms.
  • UVM Low Power - A UVC, created automatically based on a CPF file, verifying and stimulating the power aspect of the device.
  • UVM Acceleration - User-friendly interface to Palladium, implementing SCE-MI communication between the acceleration machine and the UVC running on the host.
  • vr_ad - This register and memory package is now part of the Cadence contribution to UVM e. It became open source, and is being enhanced with additional capabilities (and performance improvements, which should be great news to all of you vr_ad users).

To get a real feeling for what a "UVM UVC" is -- and how it differs from what you already know about verification components in e -- take a simple step: Run the Incisive Verification Builder, and create a UVM e UVC. Next, you can try to convince your colleagues and management that they should also start using UVM e.

Efrat Shneydor


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