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The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Comments(0)Filed under: Functional Verification, Testbench simulation, Verification methodology , SoC, SystemVerilog, IES, verification, Incisive, uvm, testbench, simulation, coverage, universal verification methodology, YouTube, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, UVM tutorial, verification tutorial, video tutorial, Stimulus, cowbell, IEEE 1800, Chinese audio, Chinese videos

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos.


  1. Interface UVC Environment
  2. Virtual Sequencer - Sequence
  3. Module UVC
  4. Scoreboard
  5. DUT Functional Coverage
  6. Testbench
  7. Test
  8. Configuration
  9. Factory
  10. Phases
  11. Objections
  12. Virtual Interface
  13. Class Library Overview

Once more I would like to thank my colleague, Yih-Shiun Lin for his great job in translating the audio. It is his voice you hear on these videos.

Besides releasing the videos to YouTube, we are also publishing them on

YouKu, the Chinese version of YouTube.

Link to YouTube Playlist (Chinese)

Link to YouKu Playlist (Chinese)

Link to YouTube Playlist (English)

Link to YouKu Playlist (English)

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer


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