Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP (ABVIP) code as part of Cadence's Verification IP (VIP) and SoC Catalog offerings. Specifically, the ABVIP code in the July 2012 release has been completely re-architected to be:
- Higher performing for both Incisive formal and simulation engines (with gains from 1.5x to ~ 10x!)
- Simpler to instantiate and configure
- Easier to use with context-sensitive IP title support in the SimVision waveform debug environment
- Inclusive of new protocols: APB4 and AXI4
Here are the details:
* The ABVIP code itself has been internally re-architected to reduce complexity, and thus provide higher performance and better quality of results. For starters, the code has been re-implemented in System Verilog Assertions (SVA) to take advantage of performance enhancements made for the SVA engines in both Incisive formal tools (Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV)) and Incisive Enterprise Simulator-XL (IES-XL). In terms of the AXI3/AXI4 titles, the complexity is now controlled by the number of outstanding transactions rather than the width of the ID bus.
* The new ABVIP is simpler to instantiate and configure than its predecessors. The user simply instantiates the correct model of the ABVIP: master, slave or monitor, and the constraints are automatically configured -- no more need for Tcl configuration. Furthermore, there are additional capabilities depending on the title selected. For example, an instance of the AXI3 Master module automatically configures the ABVIP to configure all master properties as constraints without user intervention.
* Waveform debug has been enhanced to automatically provide an IP-title, context sensitive grouping of signals in all formal counter-example, and witness waveforms. Specifically, when IFV or IEV is being used, the tools are aware of the ABVIP's presence and they create interface signal groupings to aid in the viewing and/or debug of waveforms. For selected ABVIPs, all instances of the ABVIP interfaces will have their signals available in the waveforms; and each instance will have a separate group of signals in the waveform. As is evident in the screen shot included below, this is a huge time saver when trying to view witness waveforms or debug failures.
* In addition to enhanced waveforms, for the AXI family of protocols, transaction tables are available to show the currently active transactions. As shown in the following screen shot for the AXI3 ABVIP, this feature makes it easier understand the currently active transactions and which state they are in.
In this example, you can see that the ABVIP is configured for a maximum of 2 deep transaction queue where there are 2 valid write transactions in flight, and one valid read transaction in flight, as indicated by the "Valid" column. Hence, with the waveform cursor it's very easy to deduce the state of the bus at any time in the waveform.
* The following table lists all the supported protocols and features available with each protocol, including the new AXI4 and APB4 titles. Please note the migration guides are supplied to help existing users migrate to the new ABVIP.
In summary, the new ABVIP models incorporate enhancements to improve performance, simplify instantiation and configuration, provide a more productive debug environment, and expand the catalog to include APB4 and AXI4 protocols.
R&D Product Expert Team
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Reference Link: Cadence's Verification IP Catalog