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Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

Comments(0)Filed under: Functional Verification, Testbench simulation, Verification methodology , SoC, SystemVerilog, IES, IEEE 1647, verification, Incisive, uvm, testbench, simulation, coverage, universal verification methodology, YouTube,, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, UVM tutorial, verification tutorial, video tutorial, Stimulus, cowbell, Chinese audio

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos.

The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into Chinese.

We are kicking it off with the first 12 videos titled:

  1. Introduction
  2. DUT Example
  3. UVM Environment
  4. Interface UVC
  5. Collector
  6. Monitor
  7. Sequence Item
  8. Sequence
  9. Driver
  10. Sequencer
  11. Agent
  12. Agent types

I would like to thank my colleague, Yih-Shiun Lin for his great job in translating the audio. It is his voice you hear on these videos.

Besides releasing the videos to YouTube, we are also publishing them on YouKu.


We plan to complete the audio translation for the remaining tracks in the future - So stay tuned to this blog so you don't miss any of them.


Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer


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