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DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC System Verification

Comments(0)Filed under: DAC, SoC, Mike Stellfox, verification, debug, Joe Hupcey III, interview, video, DAC 2012

R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence.  Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production.  In this interview on the floor of the Design Automation Conference (DAC 2012), Mike gives a brief snapshot of how innovations in debug automation have moved from the lab to the show floor, and how ad-hoc hardware-software SoC verification processes are breaking down, thus calling for more repeatable, automated solutions.

If the embedded video doesn't play, click here.

Question: are you seeing similar trends in your company and/or customer base?   Please share your thoughts below, or contact me or Mike offline.

Joe Hupcey III


On Twitter: @jhupcey, http://twitter.com/jhupcey

 

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