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Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

Comments(0)Filed under: Functional Verification, Testbench simulation, Verification methodology , SoC, eRM, SystemVerilog, IES, Specman, IEEE 1647, hvl, verification, Incisive, uvm, testbench, simulation, coverage, universal verification methodology, YouTube, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, UVM tutorial, verification tutorial, video tutorial, Stimulus, URM, cowbell, IEEE1800

In the world of Star Trek "resistance is futile" when you encounter the Borg. Fortunately, in verification we do not have to deal with the Borg. Nonetheless, our world provides plenty of challenges. Schedules are tight, problems are complex, and market windows are narrow. In other words, in the world of verification "inefficiency is futile" when trying to find bugs.

Subsequently, efficiency is paramount to get the job done. One angle to improving verification efficiency is to avoid redundant execution of simulation cycles. Such redundancy might exist in device configuration, linking, and programming, for example.

Depending on your situation, reducing this redundancy can have a significant impact on the simulation farm load and on debug efficiency. This can be accomplished by using a setup that leverages save, restore, and reseed effectively. These savings can be applied both for e (IEEE 1647) and SystemVerilog (IEEE 1800).

The YouTube video below, these application notes (for e & for SystemVerilog), and this archived webinar explain how this technique works in detail.

Stay efficient!

 

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

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