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Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog

Comments(0)Filed under: Functional Verification, DAC, accellera, uvm, uvm world, UVM 1.1b

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here. Cadence is happy to see this latest release maintaining the APIs and backward compatability of the UVM while improving the quality and stability of the SystemVerilog library.

Building on a decade of experience with the methodology, Cadence offers a unique solution for the UVM.  That experience is showcased in the recent series of SystemVerilog and e videos produced by Axel Scherer.  Those videos introduce the key concepts in the methodology using the Incisive Enterprise Simulator.  You can see more about the unique capabilities of the Incisive Enterprise Simulator for UVM in our DAC booth (highlighting UVM with low-power) and in our suites for more depth.

If you are going to be at DAC I look forward to seeing you there.

 =Adam Sherilog, Incisive Product Manger 



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