One of the many requests that we get from Specman/e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM-e basic tutorials. Check them out.
These e-based videos are targeted for design and verification engineers who are interested in learning about the basic concepts of UVM-e and the benefits that the e language provides.
As you may know, e is an IEEE 1647 standard hardware verification language (HVL) that is tailored to implementing highly flexible and reusable verification testbenches, leading to a significant productivity improvement. e is one of the most mature verification languages, used by specialists for advanced verification. It is, therefore, the most mature in its coupling to overall verification methodology, technology, and verification IP (VIP), and it can scale to the most complex block/unit, chip, system, and project levels.
These videos provide the basics of Aspect Orient Programming (AOP) capabilities, constrained randomization, scoreboarding, etc....
So, relax, make yourself comfortable and enjoy these videos. Hopefully, these videos will excite you enough to try out the e language on your new or existing verification project and join the elite team of Specmaniacs.
Here's a list of You Tube e videos for your enjoyment!
- Introducing UVM
- Example DUT
- UVM Environment
- Interface UVC
- Sequence Item
- Sequence Driver
- Agent types
- Interface UVC environment
- Virtual Sequence Driver - Sequence
- Module UVC
- DUT Functional Coverage
- AOP - Aspect Oriented Programming
- Signal Maps