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Get Started on UVM-e with Free Introductory Video Tutorials

Comments(0)Filed under: Functional Verification, Testbench simulation, Verification methodology , OVM, SoC, eRM, CDV, SystemVerilog, IES, e, Specman, IEEE 1647, hvl, verification, Incisive, MDV, VMM, Vera, uvm, testbench, simulation, coverage, videos, universal verification methodology, uvmworld.org, Incisive Enterprise Simulator, video, Axel Scherer, UVM training, test generation, UVC, Questa, VCS, IUS, UVM tutorial, verification tutorial, AVM, video tutorial, URM, cowbell, UVM-e, UVMe

One of the many requests that we get from Specman/e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM-e basic tutorials. Check them out.

These e-based videos are targeted for design and verification engineers who are interested in learning about the basic concepts of UVM-e and the benefits that the e language provides.

As you may know, e is an IEEE 1647 standard hardware verification language (HVL) that is tailored to implementing highly flexible and reusable verification testbenches, leading to a significant productivity improvement. e is one of the most mature verification languages, used by specialists for advanced verification. It is, therefore, the most mature in its coupling to overall verification methodology, technology, and verification IP (VIP), and it can scale to the most complex block/unit, chip, system, and project levels.

These videos provide the basics of Aspect Orient Programming (AOP) capabilities, constrained randomization, scoreboarding, etc....

So, relax, make yourself comfortable and enjoy these videos. Hopefully, these videos will excite you enough to try out the e language on your new or existing verification project and join the elite team of Specmaniacs.

Here's a list of You Tube e videos for your enjoyment!

  1. Introducing UVM
  2. Example DUT
  3. UVM Environment
  4. Interface UVC
  5. Collector
  6. Monitor
  7. Sequence Item
  8. Sequence
  9. BFM
  10. Sequence Driver
  11. Agent
  12. Agent types
  13. Interface UVC environment
  14. Virtual Sequence Driver - Sequence
  15. Module UVC
  16. Scoreboard
  17. DUT Functional Coverage
  18. Testbench
  19. Test
  20. Configuration
  21. AOP - Aspect Oriented Programming
  22. Phases
  23. Objections
  24. Signal Maps

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