Home > Community > Blogs > Functional Verification > the facts why accelerated vip is needed for soc verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

The Facts: Why Accelerated VIP Is Needed for SoC Verification

Comments(0)Filed under: Functional Verification, SystemVerilog, SystemC, VIP, verification, uvm, Palladium XP, simulation, e language, Palladium, verification IP, ACE verification, AVIP, acceleration, simulation VIP, SCE-MI, VIP Catalog, Accelerated VIP, emulation, protocol verification

On Tuesday May 15th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP).  You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP.  Good question.  This blog will answer that and explain the rationale behind Cadence's AVIP and more about our products and plans going forward.  

A key driving factor impacting verification approach is the size of the design.  Today designs commonly are in the 10's and even 100's of millions of gates.  And software size is growing at an even faster pace.  There's no respite in sight for these torrid growth rates.  So even if you don't face such verification challenges immediately, read on, because they're coming.    

Verification teams have taken notice of these facts and are adapting their approaches.  It's become a necessity to expand the set of functional verification tools employed beyond just simulation.  That's because simulation times have become excessive for SoCs, and even for many subystems.  Consequently, leading companies have adopted accelerated platforms and accelerated verification IP (AVIP) for their hardware verification. 

In addition, to tackle the expanding firmware/software development challenge, acceleration is frequently being used in tandem with a virtual prototype such as Cadence's Virtual System Platform.  This enables the CPU cycles to be run separately from the rest of the logic to maximize software execution speed.  These verification techniques are enabling leading verification teams to meet their design goals such as shortening overall product development cycle, increasing design functionality, reducing power consumption, and/or improving quality. 

Such leading companies have adopted a tiered approach to system integration and verification.  Their best practices include setting verification goals for each integration tier and selecting the verification methods and metrics to maximize those specific goals.  These include:

  • Hardware IP Development and Verification
  • Hardware Subsystem/SoC verification
  • Hardware/Software Integration and Validation

For a more detailed discussion regarding the verification approaches being employed, please see Cadence's just published Comprehensive Acceleration White Paper.

That begs the question: is simulation and simulation VIP a dead end?  Absolutely not.  Simulation has an important place in the verification continuum, but as Clint Eastwood so famously said in his Dirty Harry role "a man's got to know his limitations."  

Simulation's role is increasingly limited to IP/block verification.  That's a critical role and a key reason that Cadence continues to invest heavily in simulation VIP in addition to accelerated VIP.  But when it comes to SoC verification, the need for speed is crucial.  We've seen from customers that SoC verification requires performance gains of at least 20X over simulation.  And very commonly performance gains must be in the 100X-1000X over simulation when the full SoC is being validated and/or software is being developed.  Meeting these needs is exactly why Cadence has brought acceleration and AVIP to market. 

But be wary!   Other VIP suppliers have posited that a 4X gain in simulation VIP speed will enable its use in SoC verification.  First of all, Even if you take such speedup claim at face value, a 4X gain in VIP performance only translates to a 13% gain in overall performance.  That's why Cadence takes a very different perspective.  For more information my colleague Tom Hackett just wrote an excellent article about how testbenches and testbench languages must be properly applied and used on the right verification platform for SoC level verification.  And, unlike other unsubstantiated claims, Tom's article includes hard data and simple math to back up our positions. 

Like other accelerated VIP, Cadence AVIP uses a SCE-MI interface to connect to a host workstation.  However, that's pretty much where the similarities end.  Cadence AVIP is uniquely architected to deliver a range of performance and verification tradeoffs, all under user control. 

OK, so you're sold on the need for accelerated VIP, why should you select accelerated VIP from Cadence?  Cadence AVIP has several advantages.  A partial list includes:

  • Cadence AVIP delivers high performance. All customer engagements have demonstrated the AVIP meets or exceeds its performance targets. To achieve the high performance, the AVIP employs another unique architectural advantage: the Acceleration Optimized Core.
  • Cadence AVIP provides multiple user interfaces to enable you to use just one single AVIP for all your verification tasks. These interfaces and their uses are briefly described below:
  • Cadence AVIP supports a UVM interface for easy UVM testbench reuse in acceleration, with the same consistent user interface as the Cadence simulation VIP. This also enables the AVIP to support testbenches written in verification languages such as SystemVerilog and e.
  • For testbenches written in C or C++, the C/C++ interface is used to deliver a higher level of performance than with the UVM interface, typically hundreds of times greater than with simulation
  • It is also possible to eliminate the testbench completely using the embedded interface. With the entire design running on the Palladium platform users get the maximum validation performance. (This can also be referred to as emulation.)
  • The TLM 2 interface is used for software development and/or hardware/software co-development.

Figure 1. Cadence AVIP provides multiple user interfaces so you can use a single AVIP for all your verification needs

  • Cadence AVIP provides "knobs" enabling you to make tradeoffs between performance and verification functionality. For example, streamlined stimulus generation, checking, and coverage for UVM environments are all under user control.

Thanks for reading this far!  I suspect you're now wondering what protocols does Cadence provide AVIP for?  Great question.  Today Cadence provides AVIP for AMBA AXI 3/4, AMBA 4 ACE (including ACE Lite), PCI Express 2/3, USB 3.0, HDMI 1.4, SATA, and Ethernet 10G.  We have plans for more protocols including MIPI and DisplayPort. I encourage you to get in touch with your Cadence AE or salesperson to discuss your needs with us. 

For more information on AVIP, click here. 

Pete Heller

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.