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Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Comments(0)Filed under: Functional Verification, Low Power, Simulation acceleration, IES, Incisive Enterprise Simulator (IES), DVcon, IES-XL, Incisive, Mixed-Signal, Low-power, uvm, testbench, whitepaper, simulation, assertion-based verification, 20nm, Incisive Enterprise Simulator, gate level, gate-level, verification speed, Incisive performance, simulation speed

Its’ all about RTL simulation.  I mean gates.  I mean turn-around-time.  Project-level productivity.  Mixed-signal.  Low-power. UVM.  And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these.  Our new white paper details a systematic approach to verification performance you can use immediately at all levels from core simulation to advanced technologies and methodologies.

For certain, the most common use of simulation is RTL and gate-level simulation.  During 25 years since the start of the RTL era, Moore’s law has held true as designs have doubled every 24 months.  While the design work is still all done in IEEE 1076 and 1364 (+1800 since 2005 and now some 1666), verification productivity, predictability, and quality is now derived from an ever-increasing suite of standard languages and methodologies.  The result is that the typical simulation run today employs a wide range of features beyond RTL and gate.

That history lesson is probably common knowledge, but how to deal with the performance requirements of advanced node SoCs isn’t. Because of all the complexity, the simulator has to be measured in multiple ways to build-in the best performance.  That will give us a fast simulator, but if we run that simulator using the golden scripts we created years ago the effect on this fast engine is akin to strapping model-T tires on an F1 car. After we’ve got all the elements of our simulation balanced for performance, it’s time to dig deeper into the code we’re running on the engine.  Sure, that code is running accurately, but is it running efficiently?  The simulator is just going to execute the code we provide, so we need to profile our code and find algorithms that get the same task done but do it faster.  We introduce this last concept in the white paper, but that’s a teaser for a DVCon 2012 SystemVerilog performance paper. Stepping back from profiling, keep watching this blog stream for application notes that will help you implement the ideas in this core simulation section of the white paper.

Now that your simulations are running fast, where do you go to get even more performance?  The “Advanced Node SoC Verification Requirements” section of the white paper introduces several technologies and methodologies that, with varying degrees of investment, can provide substantial improvements in performance and productivity. If you are at or below 40nm, or planning to go there, pay careful attention to this section and the Advanced Verification Topics book to understand the options you have for further performance improvements.

When Cadence pioneered commercial simulation with Verilog-XL 25 years ago, life was simple.  Chips were designed in schematics, and RTL and gate simulation was all we needed.  Simulation has come a long way from those days and is even more relevant in today’s complex chips.  This white paper will help you understand how the Incisive Enterprise Simulator has adapted to today’s advanced node SoCs and how it will continue to scale for tomorrow.

=Adam Sherer

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