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Holiday Idea #1: Give the Gift of UVM Knowledge

Comments(0)Filed under: OVM, IES, IES-XL, uvm, Accellera VIP TSC, Incisive Enterprise Simulator, UVM training

Your favorite verification engineer has been good all year.  Thousands of tests run. Nights and weekends of debug.  So how do reward her? Why, with UVM Training, of course!

Cadence experts have trained hundreds of engineers on OVM and UVM.  These trainers have deep knowledge in both the methodology and the Incisive simulators that run it.  They track the latest activities in the Accellera Systems Initiative standards committee, and the latest releases from that group, to keep their training on the leading edge.  Each of the trainers avidly read and contribute to the UVM World forums to understand current issues and to share their knowledge.  Whether you attend a standard Cadence UVM training class or a custom one, you are in good hands.

The course begins with a short review of SystemVerilog classes and class constructs, together with an overview of object-oriented concepts and features.

The reminder of the course describes the Universal Verification Methodology (UVM) class library, which provides the building blocks and infrastructure for a verification environment, and defines a methodology to show how the class library can be used to create powerful, reusable UVM Verification Components (UVCs) based on a standard architecture.

UVM is the Accellera standard replacement for OVM (Open Verification Methodology), a class-based verification library and reuse methodology for SystemVerilog®. UVM is supported and endorsed by almost all EDA vendors, including Cadence, Mentor, and Synopsys. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology allows engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments. It also shows how to combine multiple UVCs into a full verification environment.

Learning Objectives

After completing this course you will be able to:

  • Review SystemVerilog class-based features and to examine the use of dynamic class instances to create both data objects and verification components.
  • Explore the features and capabilities of the UVM class library for SystemVerilog.
  • Define and explain a clear, proven methodology for creating reusable, scalable and robust verification components.
  • Gain hands-on experience of how the UVM class library can be used to implement a verification environment based on the methodology above.

So if you are in a bind and your favorite verification engineer has a hankerin' to stay on the leading edge, give them the gift of Cadence UVM training this holiday season. Click here for more details.

Adam Sherer


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