The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and as you can see in the image gallery below 24 customers from different 6 companies came together to share their general experiences and detailed case studies on formal and assertion-based verification (ABV). We also took the opportunity to announce and demonstrate some new technologies, share our product roadmap, and learn new requirements from the attendees to better align our R&D development with their needs.
Here are some specific highlights from our information-rich agenda:
1. "Warm-up" Demo: rapid design bring-up
To give everyone some "food for thought" and seed our later conversations, I kicked off the proceedings with a brief demo on our rapid "bring-up" flow. Specifically, I showed how Automatic Formal Analysis (AFA), Assertion-Driven Simulation (see prior post and archived webinar on "ADS"), Assertion-Based Verification IP and pure formal together can shorten the cycles of designer and verification engineers to bring-up and explore a new design without testbench.
2. Incisive HDL analysis ("HAL") overview and usage with IFV/IEV
R&D's Jianxin Bai talked about the HAL technology in general, and how its linting capabilities can be used to tee up efficient IFV/IEV runs.
3. Automated SoC iIntegration verification and demo
Peng Yu showed how formal technology can be applied to connectivity verification in SoCs via automatically generated assertions, and how this methodology out-performs the traditional simulation approach on coverage and productivity. (Ed. Note: there is an archived webinar on this topic posted here)
4. Code coverage unreachability analysis with Incisive Enterprise Verifier (IEV) demo
I had the honor of presenting the newly released coverage unreachability flow, which aims to reduce the time to coverage closure by determining the unreachable code coverage automatically by formal technology, and most important it's an integrated solution to existing simulation.
5. Writer block verification using Incisive Formal Verifier (IFV)
Legang Sun (LSI) shared his experience on applying RTL checks and AFA of IFV to the "writer" block (a block shaping the write signals to a hard disk). Those automatic checks and assertions detected design issues with very low effort, thus visibly increased the team's productivity.
6. CRG block verification using IEV (Hisilicon)
Ke Xu (Hisilicon) shared his work on Clock Reset Generation (CRG) block with ABV and IEV. He spoke about the reasons for adopting formal verification on this block and how several efficient corner case bugs were caught by IEV, and also shared feedback on how to make the tool and workflow better.
7. IFV & IEV roadmap highlights
Last but not least, Product Engineering lead Axel Scherer presented the big picture of solutions we offer today around formal verification, and shared our near term product roadmap.
At the end of the day, everyone was a little overwhelmed by so much information, but in a good way. Everyone found the presentations and demos to be of immediate, "I can go back to my desk and try this right now" value; plus they gave our factory representatives lots of valuable feedback which will definitely help us to improve our solutions.
Until the next Club Formal, happy verifying!
Principal Solutions Engineer
for Team Verify
On Twitter: http://twitter.com/teamverify, @teamverify