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Report: Formal Analysis Papers at CDNLive India 2011

Comments(1)Filed under: Functional Verification, Formal Analysis, CDNLive, ABV, MDV, IEV, formal, IFV, metric-driven verification, India, assertions, ABVIP, formal verification, assertion-based verification, ADS, Assertion-Driven Simulation, Lokesh Pundreeka

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains came together for CDNLive India 2011.  Among the attendees were over 300 design and verification professionals who focused on the functional and system verification tracks.  In this post I'll pull together some highlights from the customer presentations, with particular emphasis on the papers about formal, formal combined with simulation, and assertion-based verification (ABV).

Preface: prior to the event we were blessed with an embarrassment of riches. We received 12 very strong abstracts on formal and ABV-related topics from world-class organizations like LSI, Cisco, TI, NXP, STMicro, Freescale, KPIT, WiPro, NVIDIA and SanDisk that covered SoC integration, constraints validation, coverage closure, complex IP verification, AMBA-specific bus metric-driven verification using ABV IP, cache controller verification ... and more!  

Clearly formal and ABV were hot topics, but the program committee needed to balance it with other major industry issues like Universal Verification Methodology (UVM) adoption, low power design and verification, etc.  Consequently, our panel of judges (comprised of well known VLSI industry experts) had a very tough time to short-list only 4 formal-related abstracts along with papers covering UVM, Low Power, and high speed IP verification in the Functional Verification track.

The formal and ABV-related papers included these highlights:

* The first paper on formal and ABV was presented by Cisco Bangalore.  Entitled "Formal verification or simulation? Which way: Case study on a packet parser block", this paper explained the reasoning behind their selection of formal verification instead of simulation for verification of complex IP blocks.  Initially they had a few setbacks by choosing sub-optimal methodologies for formal verification.  But with some coaching and experience their final approach gave them visibly better returns than prior projects.  Case in point: they quickly discovered some bugs with formal that would have been very difficult to catch with simulation. The Q&A after the paper made clear that it was well received by all attendees.

* The Freescale Noida team presented a paper on an "Innovative Approach to Coverage Closure through Un-reach ability analysis Flow".  This paper explained how difficult and important it is to get code coverage closure on IP and the parent subsystems.  They explained how Incisive Enterprise Verifier (IEV) based coverage hole analysis flow helped them to quickly reach their coverage goals and pinpoint unreachable (dead) code for the designers.  As with the earlier formal paper, this one also generated lots of visible interest, and I dare say it opened a lot of eyes to the benefits of mixing formal and simulation-based approaches.

* NVIDIA Bangalore presented "Complex IP Verification Methodology using Property Driven Simulation (PDS) in IEV and Case study on memory controller".  This paper clearly highlighted how PDS (also called "Assertion-Driven Simulation") helped them in several ways simultaneously: they could define correct design constraints in much less time than before, they could overcome design complexity that was hard to process with pure formal alone (the design had over 80,000 flip-flops), and PDS-based coverage maximization techniques helped them to identify blocks for exhaustive verification.  This paper enabled each and every attendee to realize how applying formal and simulation engines together can tackle significantly higher levels of complexity without worrying much about design size.

* Last but not least, TI Bangalore presented "A Novel Approach to Coverage Completeness in Formal Checks for SOC Integration".  As usual the TI team came up with a provocative paper that addressed thorny questions like, "do I have enough assertion to check my SoC integration?", and, "Has every net/pin in the assertion cone been toggled to all possible values?"  In short, this paper clearly showed how important -- and feasible -- it is to get 100% coverage closure on all integration checks; and conversely, how less than 100% coverage can mask bugs if you ignore what the coverage holes are trying to tell you.

Again, it's safe to say that all of papers in the track were well received by audience.  However, the NVIDIA paper "Complex IP Verification Methodology using Property Driven Simulation (PDS) in IEV and Case study on memory controller" received Best Paper Award in the functional verification category.  In talking with the judges and attendees after the event, they were most impressed how the innovative combination of formal and simulation could provide so many benefits for the given effort.

Finally, if you attended the event, on behalf of all my colleagues at Cadence please accept my thanks for your active engagement!  An archive of all the papers will be posted shortly on http://www.cdnlive.com/

Warm Regards,

Lokesh Pundreeka
Technical Field Leader
Cadence India, Bangalore
for Team Verify


On Twitter: http://twitter.com/teamverify, @teamverify

 

Comments(1)

By Anu Bohra on October 29, 2011
Congratulations to the Formal team on the success of IEV and IFV and for shining through CDVLive with all the papers and awards. The spate of papers on the topic of Formal's integration with Simulation proves that it is the most interesting and challenging topic on Functional Veriification, still innovating and exciting interest in the User community.
Lokesh, I agree with your phrase".....blessed with an embarrassment of riches!"
--Anu

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