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Come See How to Connect SystemVerilog and SystemC Using UVM

Comments(0)Filed under: Functional Verification, SystemVerilog, IES, multi-language, SystemC, OVM ML, uvm, webinar

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request.  In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20.

Cadence pioneered efforts to connect a major methodology across multiple languages in 2009 with the release of OVM multi-language support.  We updated that again for the Accellera UVM 1.0 EA and we will be keeping that up-to-date with on the UVM World contributions page.  While our contribution is not part of the Accellera standard, it is a response to many user requests.  For example, we just received one this week in our functional verification forum.  Even users of competitors' simulation solutions are seeking out our multi-language capabilities.

The webinar content is dominated by technical material describing the open source solution.  We'll lead you through the overall requirements as we've collected from users and the solution we have availble for general use.  Phu will also show how the solution applies to a realistic example and, if we have time, demonstrate that solution.  There will be time during the webinar for you to ask questions to tap into the oceans of experience Phu has with SystemVerilog and SystemC.  Sorry, I just had one more pun in me.

The seminar is will be held Thursday October 20, 2011 at noon EDT and you can still sign-up here: www.cadence.com/cadence/events/Pages/event.aspx?eventid=558 

=Adam 

 

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