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Automating UVM to Tackle Insidious HW/SW Bugs

Comments(0)Filed under: SystemVerilog, IES, uvm, Accellera VIP TSC, Duolog, bugs, David Murray, universal verification methodology

You've just sat through a 2-hour program review.  The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying.  Of course, the hardware and software reviews were boring.  Blah, blah, blah about design trade-offs with some buried references to register APIs.  Your metric-driven verification (MDV) plan completely covers the spec, so you are sitting pretty.  Or are you...

Duolog and Cadence are hosting a webinar on October 11, 2011 at 9a PDT / 5p CET to discuss what happens if you don't pay careful attention, and how to correct that.  Specifically, those design trade-offs that occur during the life-cycle of all projects often lead to changes in the API between the verification, hardware, and software domains. The verification environment is constructed, in part, to understand the bit fields in the registers that make up the API. If the tradeoffs change the bit fields in any way, the verification environment must change as well. The biggest issue is that the changes must be communicated and recognized among the team members in each domain. We all can point to cases where one team makes a "simple" change that has an unexpected impact on another.

Automation can help solve this problem.  Attendees to the webinar will hear a clear description of the problem, the UVM register-package that provides a framework for the solution, and a novel technology suite that automates that solution.  Led by Duolog's CTO, David Murray, the webinar will also include a demonstration of how these insidious bugs can slip through and how the Duolog solution automates the elimination of those bugs.

For more information and to register, go to http://www.duolog.com/webinar-automating-uvm-to-tackle-insidious-hwsw-bugs/

 =Adam Sherer, Cadence


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