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Technical Tip on How to Use HDL Assertions in e

Comments(5)Filed under: eRM, SVA, e, Specman, OOP, AOP, IntelliGen, verification, team specman, Incisive, assertions, simulation, e language, assertion-based verification, Incisive Enterprise Simulator

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage.

ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification.  HDL assertions help to detect more bugs earlier in the process and closer to their source.

This feature enables the integration between the HDL assertions and the verification environment in e by providing a simple API.  The e API provides methods to enable call back registration, control and query of HDL assertions that are defined in the RTL.

Registering a callback for an HDL assertion can be done by the following simple steps:

  1. Defining an assertion callback function:
    • Derive your callback struct from hdl_assertion_cb, and implement a callback method
  2. Calling to one of the methods which register a callback on an assertion instance:
    • register_regexp_cb() - Registers a callback with the assertions that match a regular-expression input string
    • register_asserts_cb() - Registers a callback for assertions list input

There are also API methods to obtain information about the assertion attributes and to enable/disable assertion checking in the simulator.

Here are a couple of examples that demonstrate how to use the API:

Registration Callback example:

Assume you have the following assertion:

property p1;
 @(posedge clk) event1 |->  ##3 event2;
endproperty

assert_p1 : assert property(p1);

This example shows how to register a failure and success callback for this assertion:

  1. Define callback methods for failure/success:

Derive your callback struct from hdl_assertion_cb, and implement a callback method that will be executed whenever any assertion fires.

. sva_cb_err will be used when assert_p1 failed.
. sva_cb_suc will be used when assert_p1 succeed.

struct sva_cb_suc like hdl_assertion_cb
{
     callback(assert : hdl_assertion) is {
             //do something
     };
};

struct sva_cb_err like hdl_assertion_cb
{
     callback(assert : hdl_assertion) is {
             //do something...
     };
};

  1. Registering callbacks on  the assertion instance:
  • Create instances for the callback structs in stage 1.
  • Use the assert_mgr method register_regexp_cb to register callbacks with the assertions that match the "*.assert_p1" input string.
    (assert_mgr instance provides methods that let you define assertion instances as hdl_assertion types, and register callbacks on them)

   run() is also {

              var sva_cb_success: sva_cb_suc = new;
              var sva_cb_error: sva_cb_err = new;

compute
assert_mgr.register_regexp_cb("*.assert_p1",sva_cb_error,FAILURE,SVA);
compute
assert_mgr.register_regexp_cb("*.assert_p1",sva_cb_success,SUCCESS,SVA);
...
};

Query example:

At run time, when the callback() function is called, its hdl_assertion argument represents the assertion within the RTL that fired. The output from the callback() method can be customized according to the users needs.  For example, you may want to customize the behavior to output the assertion attributes and state of the target assertions.

The following example show an example of how to query an instance for it's attributes and state:

struct sva_cb_err like hdl_assertion_cb
{
     callback(assert : hdl_assertion) is {
          out("Assertion name : ",assert.get_instance_name());
          out("Assertion instance path: ",assert.get_instance_path());
          out("Assertion failure count : ",assert.get_failure_count());
          out("Assertion reason : ",assert.get_cb_reason());
      };
};


Control Example:

This example shows how to get all assertions in the design and then disable/enable assertions checking in the simulator.

  • The find_assertions method can use either a specific instance name or a regular expression to find a group of assertions. If the input string is NULL or *, the list will contain an hdl_assertion for every supported assertion in the design.
  • The disable_assertions/enable_assertions methods; disables/enables all of the assertions in the list.           

          verify()@clock is {
               var assertions_list:= assert_mgr.find_assertions("*");
               assert_mgr.disable_assertions(assertions_list);
               wait [5]*cycle;
              assert_mgr.enable_assertions(assertions_list);
              ....
           };

 

Hope you found this helpful!
Michal Nevo

Comments(5)

By Silas McDermott on September 28, 2011
This is tremendous.
Very concise and much better than the slides I've seen on the topic in the past.  I guess the big question is "when should I use this?"  For what use cases is this good for?
Thanks,
- Silas.

By Florian Mueller on September 29, 2011
Hello,
great stuff! :)
I'd really like to use it, but we are having PSL assertions here ...
Now, the HDL_ASSERT_LANG enumeration type (according to the documentation i have) has the following values:
 OVL_V1, OVL_V2, OVL and SVA
No mention of PSL ...
So my question is: Can this be used with PSL assertions?
Florian

By Michal Nevo on October 3, 2011
The support for PSL (Verilog only) is added in 10.2s70
Thanks,
Michal

By Srinivasan Venkataramanan on December 8, 2011
This is great feature. Why is it only for PSL-Verilog/SVA and not for PSL-VHDL? We are now starting a customer project with VHDL & E and PSL. Would be great to have this now!
Thanks
Srini
www.cvcblr.com

By teamspecman on December 15, 2011
Srini,
PSL-VHDL is on Specman plan, we hope it will be released in 2012.  Stay tuned ...
Team Specman

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