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Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System Realization

Comments(0)Filed under: DAC, SystemC, Mike Stellfox, debug, Trailblazer, accellera, uvm, System Realization

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers inside Cadence.  Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production.  In this interview on the floor of DAC 2011, Mike gives a brief snapshot of the migration to the Universal Verification Methodology (UVM) by customers and EDA vendors alike, how debug is becoming much more of bottleneck than it used to be, and the momentum of System Realization with SystemC overtaking traditional, RTL-centric flows.

If the video fails to play, click here.

Question: are you seeing similar trends in your company & customer base?   Please share your thoughts below, or contact me or Mike offline.

Joe Hupcey III

On Twitter: @jhupcey, http://twitter.com/jhupcey



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