One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP. Duolog is in the vanguard of creating automation to address this challenge, and in this video update Duolog's CTO Dave Murray notes new capabilities with both Cadence and ARM-centric flows, how IP-XACT has become an extensible platform, and how the UVM standard (and the UVM register package, in particular) has made everyone's life easier.
If the video fails to play, click here.
Note: in case you were wondering, Duolog's booth was hopping -- an observation confirmed by their Marketing director who said they had a 4x increase in booth traffic over last year. Beyond the updates noted in the video, they presented jointly with us on:
* Earlier TLM2.0 IP & Systems using Socrates and Cadence Virtual System Platform
* Faster Fabric Integration using ARM AMBA Designer and Socrates
* Time-saving UVM Testbench Automation using Socrates and Cadence Incisive
Duolog has a great track record of posting detailed app notes and white papers on the "Technical Documents" page of their site. Thus, if you missed DAC some of the above topics are already addressed on this page, plus I'd expect new updates shortly.
Happy IP Integration!
Joe Hupcey III
On Twitter: http://twitter.com/jhupcey, @jhupcey
Duolog's main website: http://www.duolog.com/
White paper on how Duolog's Socrates Chip Integration Hub Supports the EDA360 Vision
Even more white papers on IP integration and related automation: