I was at the Design Automation Conference (DAC) last week showcasing our latest, greatest Incisive Enterprise Simulator (IES) performance features in the demo suites. In my "off" time, I was in our DAC booth meeting customers and discussing our advanced verification solutions. I ran into a long-time SystemVerilog user who had been using that language since the AVM methodology days years ago. He mentioned to me that he had attended the Accellera UVM Workshop and was surprised to learn that the Universal Verification Methodology (UVM) was derived from the e Reuse Methodology (eRM) and that the e language was, to this day, still the most productive verification language in the industry. Before the workshop, his impression seemed to be that, since e has been around for so long, surely it must be an antiquated verification solution.
I thought about this a bit more and can see why he may have thought this. e was invented in 1992. Next year, it will be turning 20. 20 years is a long time. A really long time in the EDA world where newer technology tends to render older technology obsolete (Think of what Verilog did to schematic capture, or what C/C++ will do to Verilog in the coming years) and change seems constant.
What many people do not know is that, since the e language was developed specifically for hardware verification (a world of constant changing specs, features, tests, etc.) it was built for change. Yoav Hollander created a verification language in 1992 based on Aspect Oriented Programming (AOP) techniques that allowed engineers to model their verification environments with as many details as possible up front (typical OOP flow), while allowing for users to tweak and tune the environment over time through layering on additional functionality in a non intrusive way (AOP). The result was an incredibly streamlined and powerful language that allows for code to be managed and maintained in ways unthinkable using any other verification solution, including the best of the best of today's solutions.
Is e old? Yes. Is it outdated? Definitely Not. Other languages are still trying to catch up. Remember, SystemVerilog was based on donations from other languages in the early 2000's, all of which did not have the productivity advantage of e at that time. UVM brings to SV some of the features of e -- however, until the overhead of the class libraries is pulled into the language itself and full AOP capabilities are added, it has a long way to go.