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DAC Preview: Make Assertions Come Alive with Assertion-Driven Simulation

Comments(0)Filed under: Functional Verification, Formal Analysis, DAC, PSL, SVA, ABV, IEV, formal, assertions, formal verification, Chris Komar, assertion-based verification, Joe Hupcey III, Tom Anderson, ADS, Assertion-Driven Simulation

While Assertion-Based Verification (ABV) has been around for many years, ABV has largely been a passive exercise.  For example, assertions can monitor behavior in a simulation environment, model a formal analysis environment with constraints, or provide targets for formal proofs as checks or covers.  This is all very useful and good.  However, assertions are passive objects in these cases.  This means that in simulation you only get information about the assertion when it "fires."  And with Formal, you only get meaningful results or an associated waveform if a proof converges. ... Until now!

There is a new way of using assertions which makes them literally come alive.  In short, with this new technology you can turn assertions into active objects that can drive a DUT by generating stimulus automatically.  In other words, the behavior captured in assertions can be used as constraints to generate random stimulus. We call this Assertion-Driven Simulation -- "ADS," for short.

The advantage of ADS is that you can start interacting with assertions very quickly and get instant feedback. You can generate meaningful waveforms and start debugging your DUT, your environment, and your assertions -- all before a testbench exists, or the first formal proof is kicked off.  Instead you get a sense of the operation of your DUT right away by viewing waveforms.  Consider the following example:

Figure 1: Waveform generated by Assertion-Driven Simulation (ADS)


Figure 1 above shows stimulus generated by ADS for a DFI2.1 (DDR3 PHY) interface. The waveform snippet shows a read access followed by two write accesses on DFI.  This waveform has been generated by just adding 4 DFI assertions to a DUT and pressing a button.  It enabled the immediate debugging of the device.  Again, no testbench or proof was needed -- the tool automagically derived the stimulus from the assertions and the engineer was good-to-go!

An obvious application for ADS is early in a design project to bring-up a block.  Instead of creating some throw away RTL to do a sanity check of the block, with a few assertions designers can get a sense of whether the DUT is on the right track very quickly and effectively using familiar, waveform-oriented debug techniques.

Additionally, there is another, more subtle application of ADS: it's also very beneficial in the setup of complex formal verification environments.  The formal verification engineer can use ADS to make sense of all the constraints, the block initialization, and the ABV environment in general.  Field experience with ADS by formal users has proven that an ADS flow can be a very beneficial step before moving to full-up formal proofs, preventing many issues that stem from an inaccurate environment setup.

Bottom-line: Assertion-Driven Simulation, a/k/a "ADS" for short, can increase the value you get from assertions significantly (in a real sense, almost for "free") by making them active drivers and enabling low cost stimulus and waveform generation.

Happy verifying!

Axel Scherer
R&D Architect
for Team Verify

P.S. An administrative note about DAC 2011 in San Diego:
While the various Incisive Verification-oriented suite presentations and demo pods briefly touch on this topic, for more detailed information on this capability seek out Team Verify members Chris Komar, Tom Anderson, or Joe Hupcey III who will be at the show.  Of course, feel free to post a comment below today!



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