Home > Community > Blogs > Functional Verification > dvcon are you sure it s not uvmcon or msvcon
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DVCon? Are You Sure It's Not UVMCon or MSVCon?

Comments(0)Filed under: Functional Verification, DVcon, verification, Mixed Signal, Mixed-Signal, accellera, uvm, EDA360, MSV, random test

As I write this, I've just returned from the most important conference and tradeshow of the year for functional verification: DVCon in San Jose. The "DV" officially stands for "Design and Verification" but most people think that it means "Design Verification" since the focus has been almost entirely on functional verification in recent years. This week's conference was dominated by two big themes -- the brand-new Universal Verification Methodology (UVM) standard from Accellera and the increasing attention paid to mixed-signal verification (MSV). I heard several people joke that perhaps DVCon had become "UVMCon" or "MSVCon" this year.

My colleague Joe Hupcey has done his usual fine job of documenting DVCon in words and pictures and I'm sure that there will be lots of other blog posts from our attendees. I'd like to focus on just a few aspects of the show. First, I have to say that UVM ruled the day. Accellera approved the UVM 1.0 standard just last week and then made the UVM library and user's guide available for download on the first day of the conference.  The conference opened with an Accellera-sponsored UVM workshop that was packed to the walls. About 180 attendees heard vendors and users provide insight into the new standard and its enormous benefits for the industry.

There were more than a dozen additional talks and panels on the UVM, so clearly it was the hottest topic. But mixed-signal verification was not far behind. As per EDA360, most advanced-node chips will have both analog and digital content, requiring effective verification of the complete mixed-signal design. There were more than a half-dozen papers on this topic as well as a Thursday lunch panel sponsored by Cadence. The panel featured both vendors and users discussing how digital verification techniques such as planning, assertions and coverage are making their way into the analog realm as well. The users also described some of their current and upcoming verification challenges, encouraging the vendors to lead with solutions.

I had the pleasure of participating in a "Birds of a Feather" (BoF) discussion on Monday evening with representations from NextOp, CVC and Breker plus an animated audience. The topic was "Strategies in Verification for Random Test Generation" which naturally involved the UVM as well as techniques to expand beyond the simulation testbench for more effective stimulus generation and verification coverage.  I'll save the details of that session for my next post since I want to do the topic justice.

I also spent quite a bit of time on the exhibit floor, which had more buzz than I've seen in several years at DVCon. There were a bunch of start-ups exhibiting for the first time and from what I saw they attracted lots of interest. We ran an "EDA360 Passport" promotion in which anyone who visited all of our listed partners was entered into a prize drawing. That was a lot of fun; another key tenet of EDA360 is that no one company can do everything and a vibrant ecosystem is critical. It was nice to recognize our partners and offer attendees an incentive to visit all of our booths and see a broad view of interlocking verification solutions.

It was a really good show, well organized but structured with enough time to talk to customers, partners, friends and even competitors. I hope to see you all at DVCon next year!

Tom A.

The truth is out there...sometimes it's in a blog.

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.