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Being a Part of Something Truly Remarkable - UVM

Comments(0)Filed under: Functional Verification, IES, Incisive, uvm, Accellera VIP TSC, EDA360, Mentor, Synopsys

For just over two years I have had the honor of playing a role in a dramatic example of EDA360 in action --  the creation of the Accellera UVM standard 1.0. I could not be more proud!

Many will measure UVM 1.0 in terms of features, but it is much more than that.  It represents a different way of conducting the business of verification in today's electronics industry.  Our business is changing -- the cost of finer process node is centralizing IC manufacturing around just a few companies.  At the same time, the number of project teams and companies involved in the creation of an SoC is growing due to the convergence of algorithm, software, digital, and analog design needs at the new process nodes. The very industry that EDA serves is creating consortiums and building partnerships because it knows that no one company can go it alone any longer.  EDA has to follow this lead.

The Accellera Verification IP Technical Subcommittee (VIPTSC) was created in 2008 with a mission standardize industry-wide reuse.  Now companies will be able pull from a single, worldwide talent pool of verification engineers trained on one methodology.   Those engineers will be ready to take verification components from other organizations without the rewriting and/or layering expense of the past.  Even within the UVM itself, the verification IP can be repurposed across teams and from block to system without being rewritten. With verification labor costs per SoC forecast to reach $38M at 22nm (Source:  I.B.S. July 2010), the higher labor productivity enabled by the UVM will lead to higher profitability.

All of this was achieved in just over a year of development that pooled 300+ engineers representing 46+ EDA competitors, IC company competitors, service providers, and other members of the community. As secretary of the committee, I not only had a ring-side seat, but was able to help guide schedules and internal/external communications.  Along the way I got to know Adiel, Allan (sorry, Gordon :-) ), Ambar, Dennis, Fitz (slide master after my own heart :-) ), Hillel, Janick (he's a great short-order cook too!), JL, John, John, John, Mark, Sharon, Stan (Obi-wan Krolikoski :-) ), Tom, Yatin, and many others.  And we didn't negotiate the lowest-common-denominator.  We built the best. Wow.

"EDA360 will close the profitability gap through integration-ready IP creation, integration, and optimization." With the UVM, EDA is stepping up as a team.  I couldn't be more proud!

 =Adam Sherer

More information on the UVM 1.0 content.

Customer plans for migration.

Cadence Silicon Realization leveraging the UVM

 

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