Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely complex and, as a result, verifying every feature, in every mode of operation, under all conditions is extremely difficult to achieve. Achieving high DUT coverage is getting very challenging. Companies are employing very large compute farms capable of running thousands of simulations in regression runs in hopes of converging on their coverage. These regressions can take several days --> weeks to complete. Some customers need to run seemingly infinite numbers of cycles to hit their entire DUT space to achieve high coverage results.
As many verification engineers can relate to, the simulation times are increasing significantly in length too due to the complexity of the SoC and the interaction of individual blocks within the SoC. The time required to compile large amounts of code is no longer insignificant. While compiling the code can result in faster runtime simulation, many users still choose to load their verification environment code and run in interpreted mode for the improved debugging benefits. This translates to long turnaround times when debugging or when developing new tests.
Simulation-based functional verification involves a multitude of tests that together constitute the regression suite for a given DUT. Each simulation run usually involves DUT bring-up phases, for example, for the reset procedure, register configuration, link training, etc. Bring-up time can take up a significant portion of the overall simulation time for such tests. However, existing verification practices do not take advantage of this commonality between runs. The same bring-up phases are run over and over for each of the tests, contributing nothing to overall coverage, and consuming valuable time and resources. Moreover, when a test fails during regression, the debug session needs the go through the same bring up process yet again, with significant impact on debug cycle efficiency. This initialization of the design can vary from minutes --> hours --> days.
Debugging simulation failures can also be very tedious and time consuming and this is the area where verification engineers spend the most amount of time during a project. This is especially true if a failure occurs very late in the simulation run (e.g. hours or days). Getting to the point of failure consumes significant cycles and, since identifying and isolating a bug correctly can takes several iterations, this leads to many wasted simulation cycles. If the point of failure can be reached significantly faster, bypassing uninteresting functionality along the way can achieve a significant productivity boost.
Specman Advanced Option Addresses Key Productivity Concerns
To address these customer verification challenges, Cadence announced a new product called Specman Advanced Option in a Press Release Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design on Monday, January 10th. This new Option works with either the Cadence Incisive Enterprise Simulator (IES-XL) or with the standalone Incisive Enterprise Specman Elite® Testbench product for customers who want to use it with other 3rd party simulators.
The New Specman Advanced Option can improve the verification engineer's overall verification productivity by 40% - 60%. This can be achieved through 3 key features included in the Specman Advanced Option:
1) Multi-Core Compilation - The ability to spawn the compilation of e code on multiple processors in parallel
- Reduces compile time significantly, shortens debug cycle and time to first simulation
- Close to xN (N= # cores) speedup in compilation time
2) Dynamic Test Load and Reseed - New advanced functionality that leverages the existing "save/restore" functionality. Allows the user to run to an interesting point, save the state, restore the state later with different seed and/or load additional e files
- Any test that needs to be run repeatedly to get to a specific stage followed by randomized testing will greatly benefit from reseeding
- Shortens simulation/regression run time significantly. Save hundreds of hours of simulation time using the Dynamic Load/Re-seed capability
Dynamic Load and Reseed enables the following flow:
3) Debug of Compiled Code - Ability to debug in the compiled or the interpreted mode
- Compiled code executes much faster, reducing simulation time hence, reducing debug time
Overall customer engagements have shown that the Specman Advanced Option can improve the overall customer productivity by 40% - 60%. Specman Advanced Option is a key productivity enhancer offering significant performance improvements. Typical productivity gains have resulted in the following:
For more details, contact your local sales team or your local Specman/e Application Engineer. Additional technical collateral as well as free, hands-on workshops are also available upon request.
Kishore Karnane / Corey Goss