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Applying Digital-Centric Verification Methodologies to Analog

Comments(1)Filed under: Functional Verification, Low Power, System Verification, AMS, Incisive Enterprise Simulator (IES), Real Value Modeling, Mixed Signal Verification, Mixed-Signal, RVM, metric-driven verification, IP modeling, SoC ConnectivityA majority (if not all) SoCs today are mixed signal. Increasingly, the analog and digital portions of the design are inseparable. It is not possible any more to decompose them into separate analog and digital functions. Nothing can be treated as a black box and handed off to the other side. The new world is a complex, multilayered fusion of the two disciplines where the boundaries are getting fuzzy and the interactions are complex and poorly modeled. This requires an integrated mixed-signal environment.

A performance failure is generally not fatal because the system development can usually continue while the IC is re-spun for performance improvement. However, functional failures in a design can result into multiple design iterations (re-spins). These are usually at great expense in terms of non-recurring engineering costs (NRE) and missed market windows. "Top Level Verification" is one of the most critical challenges for our customers in mixed-signal verification. To ensure the reliability of the mixed-signal verification results, the first step is to integrate the analog and digital mixed signal environments. Figure 1 illustrates the integrated mixed-signal verification environment offered by Cadence Design Systems

Figure 1: Integrated Mixed Signal Verification Environment

Other mixed-signal verification challenges that customers have identified are:

  • The mixed-signal verification task is growing exponentially
    • Need to generate analog blocks in a digital context
    • Need to validate behavioral blocks to transistor level specifications
  • Pin connectivity errors cause majority of re-spins
    • Need to avoid errors like pin connection errors, inverted polarity, incorrect bus order, connected to wrong power domain, etc.
  • Analog simulation performance limits mixed-signal SoC verification
    • Support for different levels of abstraction for full chip verification is mandatory
  • Lack of structured handoff between analog design and digital verification environments
  • Advanced low-power techniques are introducing new verification challenges
  • Digital designers need to peek into the analog world and vice-versa
    • Interoperability of the tools/flow is a must

Digital-Centric Mixed-Signal Verification

Cadence provides a digital-centric mixed-signal verification (DMSV) environment to address the verification challenges listed above. This verification environment targets customers using digital-centric use models. It refers to mixed-signal verification using digital simulators only. In another words, it delivers the mixed signal verification performance very close to digital speeds. This methodology is targeted for high performance mixed signal verification for full-chip verification. Due to its digital-centric use model, it can be targeted for high volume, digital-centric nightly regressions tests.

Digital-centric mixed-signal verification leverages Real Number Modeling (RNM) so that users can perform verification of their analog or mixed-signal designs using discretely simulated real number models. This allows the simulation to only use the digital solver, avoiding the slower analog simulation and thus enabling intensive verification of mixed signal design in short period of time. The tradeoff between simulation performance and accuracy has to be considered in the context. RNM also opens the possibility of linkage with other advanced verification technologies such as metric-driven verification without the difficulty of interfacing to the analog engine or defining new semantics to deal with analog values. Overall, the DMSV technology provides five key benefits to enable customers to perform a top level SoC verification:

1. A strong bridge between analog and digital environment

The DMSV technology builds a much needed bridge between analog and digital communities by providing them a model/mechanism that works seamlessly in their native environment.  DMSV models are fully compliant with analog as well as digital verification environments. Their complete portability between the two environments eliminates the risk of any manual interventions or modifications to the designs to take them from one environment to other.

2. Compelling value addition to digital verification coverage

The DMSV models offer a much needed accuracy (of real numbers) in the digital verification environment. This allows for a much more accurate representations and verification of designs including multiple power-supply sensitivities. This allows for improved verification coverage for critical silicon bugs.

3. Performance improvement to analog design and verification process

The DMSV models provide a fast and reasonably accurate way to model analog behaviors. This allows users to perform full chip transistor level simulations by replacing some blocks with DMSV models to accommodate the capacity and speed requirements.

4. Enabling seamless integrations of blocks

DMSV technology provides key features like Coercion that allows for seamless integration of models/blocks written in various other languages/abstractions (such as SV-real, VHDL reals etc.) to be integrated and verified without needing any manual changes or painful design setups or workarounds.

5. Metric Driven Verification with DMSV

The DMSV technology enables a real number based more accurate metric driven verification by leveraging the digital verification environment, testbenches and monitoring methodologies like assertions and coverage.

DMS Option to Incisive Enterprise Simulator Technical Features include:

  • Wreal to electrical connect modules
  • Support for wreal arrays
  • Support for wrealXState and wrealZState
  • Support for multiple wreal drivers and resolution functions
  • Support for wreal table models
  • Ability to connect a wreal to a VHDL real signal or SystemVerilog real variable
  • Automatic "type-casting" to wreal when a wire is hierarchically connected to a wreal, SystemVerilog real variable, or VHDL real signal

For more details, contact your local sales team or application engineer. Additional technical collateral as well as free, hands-on workshops are also available upon request.

Kishore Karnane / Abhi Kolpekwar

Comments(1)

By ifpk454 on February 6, 2011
The issues not discussed here are
- Wreal model generation
- verification of the wreal model against the schematic
- additional resource required to develop and verify the wreal models
Using the schematics directly from the analog design team and simulating with them using incisive and AMS has it's limitations that you point out, but it reduces the barrier to entry for SoC teams to start performing mixed signal simulation.
Does the DMSV methodology help improve Mixed signal verification productivity as well as performance?

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