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Infinite Playbook for the Verification Superbowl

Comments(0)Filed under: Functional Verification, OVM, SystemVerilog, IES, Incisive Enterprise Simulator (IES), Incisive, debug, multi-core, uvm, Accellera VIP TSC, EDA360, Silicon Realization, simulationIts 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz.  What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh your drive, route the bugs, and win the verification Superbowl.

Even before the snap you need to check the environment statically to eliminate bugs. The 700+ rules in the HAL lint support were expanded with new coding and structual checks, as well as the integration of the eAnalyzer capabilities.

Once the ball is snapped, you need to get the simulation up and running fast.  New in the Incisive release is multi-core code generation, which speeds compilation times of designs that use gate libraries with many unique cells up to 1.2 times.  Elaboration has also been tuned, tapping specific user test cases in both gate and RTL abstractions.

Now that the simulation is running, you can really apply the new features regardless of the abstraction of the verification.  Roughly 2/3 of you are running the OVM using transactions in your testbench to abstract the signals in your design.  Cadence has over a dozen large user environments in-house that we are using to tune performance.  In the simulator, the result is an average 1.3 times gain for no code change.  However, this effort has also uncovered a series of best practices that we have applied with users to improve performance up to 10 times. All of this helps you achieve silicon realization convergence faster.

With the emerging UVM 1.0 based on OVM, the best OVM solution provided by Incisive is now the best UVM solution. As a result, the performance improvements for the OVM also apply to the UVM.  UVM 1.0 will build on the UVM 1.0 EA from May with several new features, and all of that code is running in the Incisive simulator now so you can move to the new release confident that it is ready for the UVM. You can learn more about this best UVM solution from one of our genIES, Kathleen Meade, in this webinar.

If you are running a pre-tapeout gate simulation, this Incisive update will help you as well.  You'll find gains up to 4 times depending on your configuration and foundry library.

With the results pouring in during simulation or in post processing, you'll need a debugger -- the best debugger -- to sort through the data to find the bugs.  SimVision is that debugger and has an array of new features that our colleague, Jim Kjellsen, will detail in a separate blog.

So you run your play, win the game, and get some time with raw silicon as you lounge on a sandy Hawaiian beach.  As you reflect on the last play that enabled verification convergence, you think "that was too close."  Another key part of the 10.2 release is an expanded and updated Incisive Verification Kit.  This clear source design includes a verification environment updated for low-power, UVM reference flow, eRM, TLM, and more.  As you pour through the manuals, you'll gain new insights into new plays you can run.

What's in your verification playbook for 2011?

=Team genIES

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