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How Do You Debug Your Testbench when it Won’t Stand Still?

Comments(3)Filed under: Functional Verification, OVM, Incisive, debug, SimVision, uvm, bugs, testbench, whitepaper

The task of debugging a simulation problem in your design can be a difficult and time consuming task.  These days, the verification engineer must also be able to debug very complex SystemVerilog testbenches too.  This becomes difficult because of their dynamic nature -- they just won’t stand still.  So what can you do?

 

Companies have been forced to put a lot more time and effort into verifying today’s complex designs by using regression farms running a large number of tests with constrained random stimulus to exercise the design and measure coverage.  This whole process, what I like to call the Verification Machine, can do massive amounts of simulation once it is up and running.  All of this technology is being put to use in hope of finding the bugs in the design.  However, this Machine comes to a screeching halt when it is interrupted by a simulation failure.  But why did it fail?  Was it the design or the testbench that caused the failure?

 

In the past, users relied on simple mechanisms such as $display and print() statements to help them see what was going on in the testbench.  With today’s modern SystemVerilog class-based testbenches, which can easily contain more code than the design, this just isn’t practical.  Not only would it be a lot of additional code for these $display and print() probes, but any change to them forces a recompile.

 

SimVision, part of the Cadence Incisive Enterprise Simulator, has the capabilities built into it to be much more efficient in testbench debug.  With SimVision you can browse the testbench hierarchy and configuration, record the transactions, view them in a stripe chart, set breakpoints and debug the constraints.  This debug and analysis can be done with an interactive simulation or in a post processing mode.  However, for post processing it’s a little more complicated since the testbench is not static in the newer methodologies such as OVM and UVM.

 

A new whitepaper is available, “Post Processing Your OVM/UVM Simulation Results,” on this topic.  This whitepaper details the process of how to gather the necessary information from the simulation to be able to do the testbench debug in a post processing mode.  You can access it here:

 

http://www.cadence.com/rl/Resources/white_papers/post_process_UVM_wp.pdf

 

Good luck in getting your simulation failure resolved and your Verification Machine back up and running quickly toward verification closure of your design.

 

Jim Kjellsen

 

 

 

Comments(3)

By horace on January 5, 2011
The white paper is great, but I have one question.
I couldn't find the uvm_phase tcl commands in IES9.2.  Do I have to setup ncsim to use those tcl commands?  Thanks.

By jimkje on January 5, 2011
The uvm_phase commands are part of the uvm install in the release.  Version 9.2-S32 is the first release that includes this in the install.

By horace on January 16, 2011
hi jim,
I just moved to 10.2, but I still couldn't find the uvm_phase tcl commands.
thanks.

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