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New UVM Book Is For You And U But Not Ewe

Comments(0)Filed under: Functional Verification, Testbench simulation, OVM, eRM, SystemVerilog, OOP, Register Package, IES-XL, TLM, accellera, uvm, Accellera VIP TSC, EDA360

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM. Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike some books about earlier methodologies, it never assumes verification engineers are sheep that can only follow simple examples.

The book starts out with the basic UVM concepts, many of which are well known to OVM users but may be new to VMM users and others.  The first few chapters introduce engineers familiar with directed verification to object-oriented programming (OOP) concepts, the UVM library, and the elements of a UVM verification component (UVC).  If you are a novice verification engineer, these chapters create a critical framework of knowledge enabling you to understand both why the component is built the way it is as well as how to do so using illustrations and step-by-step procedures.  This comes to bear in Chapter 7 where the component is applied to a verification environment and your earlier effort results in the simple test interface that the consumers of the UVC -- both designers and other verification engineers -- use to create the verification environment. 

Chapters 8 through 10 then dive into more advanced concepts including sophisticated layered protocols, applying a register package like the example one contributed by Cadence (Accellera will provide a UVM register package in the future, but not yet with UVM 1.0 EA), and scaling to system-level verification using the UVM. The book concludes in Chapter 11 with a look forward to UVM 1.0, though the most current information on that topic can be read on UVM World.  With the content in this book, you will not be a "ewe" sheepishly following simple examples, but a verification wolf ready to devour any challenge!

The biggest value to individual project teams and the industry is the "U" in "Universal."  It's widely understood that the UVM library is a tool from which to build verification IP (VIP), but that VIP can be built in multiple ways.  By rallying around the Universal Verification Methodology, the ecosystem will gain consistency, reusability, and scalability critical to the profitability of each and every project.  This EDA360 concept was proven over the last decade with the vibrant ecosystems around eRM and the OVM, and is critical to the one emerging for the UVM.  In fact, it is this consistency that frees experts to innovate new verification concepts on a solid foundation extending verification to low-power, mixed-signal, system-level, and more.

This new UVM book is available immediately in hard copy here. An e-book will follow soon afterwards. We also encourage UVM users to work with a skilled trainer such as those from Cadence and Doulos.  You also may be interested in reading the new TLM-Driven Design and Verification Methodology book, which discusses the user of the UVM to verify SystemC TLM designs.  And finally, keep coming back to the UVM World forums for news, questions, and answers from the whole UVM ecosystem.

=Adam Sherilog

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