Home > Community > Blogs > Functional Verification > why the uvm is ready for production use today part 3
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Why The UVM Is Ready For Production Use Today -- Part 3

Comments(0)Filed under: Verification methodology , OVM, VIP, uvm, Accellera VIP TSC

This is the final installment of my blog posts based on the three common questions I heard at DAC regarding the Universal Verification Methodology (UVM). I've already answered the questions "What does the UVM mean for the future of the OVM and VMM?" and "Why is the first release of the UVM labelled as "Early Adopter (EA)?"

The third and final question that I'd like to address is "Will there be a UVM e and UVM SystemC?" Actually, there were a few variations on this question, including "I'm a user of OVM e [or OVM SystermC], so how can I move to the UVM if it only supports SystemVerilog?" The same answer will suffice for all the variants.

At DAC, Cadence clearly committed to provide base-class libraries and documentation for e and SystemC versions of the UVM, just as we did for the OVM. We believe strongly that verification methodology need not be language-specific. Most of the techniques and guidelines for building reusable verification testbenches, verification IP, and models are equally applicable to all three languages.

This answer will lead some questioners to refine their query to "Will Accellera even release a multi-language UVM?" I'm not in the position of speaking for Accellera, but I understand that there are other members of the VIP Technical Subcommittee (VIP-TSC) who would like the UVM to evolve to be a multi-language methodology so perhaps this will come to pass.

In the meantime, the very close relationship between the OVM and the UVM means that you can easily use existing OVM VIP (in any of the three languages) in a UVM SystemVerilog testbench. We live in a multi-language verification world, and so the OVM and the UVM were architected for multiple languages from the beginning.

So that's it! I answered the three big questions from those who were a bit hesitant to jump on the UVM juggernaut. If you have any additional questions that I didn't address, please post them in a reply Otherwise, visit UVM World and join your peers in embracing the UVM for your next verification project; you'll be glad you did.

Tom A.

The truth is out there...sometimes it's in a blog.  





Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.