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Why The UVM Is Ready For Production Use Today - Part 2

Comments(0)Filed under: DAC, OVM, VIP, EDA, uvm

In my last blog post, I talked about the three most common questions I heard at DAC from people who had some concerns about moving to the Universal Verification Methodology (UVM). I already addessed the question "What does the UVM mean for the future of the OVM and VMM?" by noting that the OVM developers are moving their focus to the UVM.

Today I'd like to address the second common question: "Why is the first release of the UVM labelled as "Early Adopter (EA)?" Again, the answer to this question is part of the reason why the UVM is ready for production use on real projects today and why verification teams should not hesitate to adopt it.

The short answer to the question of why Accellera decided to call the first release "UVM 1.0 EA" is that some members of the VIP Technical Subcommittee (VIP-TSC) want to add a few more features to the UVM before declaring it as "1.0" level. The list is not yet finalized, but it might include such features as a register package, simulation runtime phases, and TLM 2.0 support.

The issue, of course, is that "Early Adopter" is making some potential UVM users nervous. They are wondering whether the UVM is really ready and whether the base-class library code is well-tested and stable. Some are also worried that the UVM 1.0 release will look very different, thereby obseleting work done with the UVM 1.0 EA version.

Fortunately,VIP-TSC Co-Chair Tom Alsop posted a terrific response on the UVM World Forum. He clarified that "only the 3 new features listed in the release notes should be consider[ed] as ... Early Adopter" and that the rest of UVM 1.0 EA is based on the very stable OVM 2.1.1 release. He also said that "UVM 1.0 will be backward compatible" with UVM 1.0 EA with few, if any, exceptions.

Since I've been lobbying hard for a high degree of backward compatibility throughout the entire OVM-to-UVM transition, I am delighted to see this commitment from Accellera. With the first two common questions answered, SystemVerilog OVM and VMM users have absolutely no reason not to consider the UVM now. In my next post, I'll deal with the multi-language needs.

Tom A.

The truth is out there...sometimes it's in a blog.  

 

 

 

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