In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been a lot of hard work by many members of the TSC since December of last year when the OVM was chosen to be the basis of the UVM, for some of us, the road to get here was actually much longer - nearly 10 years in the making. Don't let the "Early Adopter (EA)" tag on this first release of UVM give you the wrong impression, since it is based on testbench best practices that have been used by hundreds of verification engineers for nearly a decade.
It all started back in 2000 at a small start-up named Verisity. At that time, Verisity was having success selling Specman, for building constrained-random, coverage-driven testbenches. However, there was a significant challenge to ramp up new engineers on how to build these powerful, automated verification environments, and there were a lot less verification engineers than today (still not enough in the industry but that is another story). Moshe Gavrielov, as the CEO, decided to form a team called "Specware" who created the first set of verification methodology best practices in the form of software verification patterns in the "Verification Advisor". This was a great start for helping proliferate verification knowledge transfer, but it was not enough. Verisity had a lot of very savvy Verification AEs and customers, and every AE and customer was very creative in developing their own style of testbench - so creative, in fact, that it was practically impossible for anyone other than the original developer to comprehend the code that had been written, which made testbenches difficult to reuse and a lot of effort to write and maintain.
This lead to Yoav Hollander, the founder of Verisity, working with the Specware team, AEs, and some expert customers and consultants to take things a step further by building the first commercial methodology for constructing reusable verification components, known as the e Reuse Methodology (eRM). (I was fortunate to be one of the AEs involved in this effort.) The eRM was built by generalizing all the best practices that had been accumulated by that time. It included most of the key methodology concepts you see today in UVM including:
Interface verification components as the base reusable building blocks
Env/Agent architecture with separate BFM/Driver from Sequence_driver/Sequencer and monitor
Common configuration options like active/passive agents, signal port maps, etc...
Sequences for building constrained-random, reusable stimulus and having a common test-writer interface
Debug messaging and logging and control of messages
Here is an "old-school" slide from when we introduced the original vision of eRM:
Over the next several years, the eRM was adopted by hundreds of customers, and Verisity used the eRM to build the first commercial e Verification Components (eVCs) for standard protocols like PCI, AHB, and Ethernet. Many additions were made to eRM including a register package (vr_ad), module to system reuse, and HW/SW co-verification, and customers across the world continue to adopt and apply eRM on projects today.
When Cadence acquired Verisity in 2005, SystemVerilog was starting to gain attention as a second standard verification language, so several of the original eRM experts decided to adapt the eRM concepts to build a SystemVerilog verification methodology, which was released as the URM in 2006. The URM was a single verification methodology for both SystemVerilog and e, including support for multi-language environments. At the time Mentor had developed the AVM base-class library for SystemVerilog, and since both Cadence and Mentor were making their libraries available via open-source, and they shared a common communications approach based on the OSCI TLM standard, the two companies decided to unify AVM and URM to create the OVM, which was released open-source on OVMWorld in January of 2008. The OVM has been a very successful joint development effort and Cadence not only managed to bring to it all the mature, proven concepts of eRM, we also contributed a number of SystemVerilog specific features including:
The factory & configuration mechanism
Field automation, message macros, & objection mechansim
A robust register package
Multi-language interoperability with OVM e verification components and OVM SystemC models
OVM has been a huge success in the market, which eventually lead the Accellera VIP TSC to choose it as the basis of the UVM, It has been a long time in the making but the core methodology concepts from eRM to URM to OVM to UVM have remained consistent with small refinements along the way. So, as we celebrate the "birth" of UVM today, we also celebrate the 10 year anniversary of the of eRM - a bit corny but appropriate...