Home > Community > Blogs > Functional Verification > team verify s 2010 cdnlive munich guide
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Team Verify's 2010 CDNLive Munich Guide

Comments(0)Filed under: Functional Verification, Formal Analysis, metric driven verification (MDV), CDNLive, PSL, SVA, ABV, MDV, IEV, formal, Contributions, IFV

We're excited to report that next week's annual CDNLive! event in Munich will feature many papers of interest to end-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV"), or anyone interested in either "pure formal" verification, integrated formal analysis and simulation verification, and assertion-based verification (“ABV”). 

An overview of the conference with info on how to register is here: http://www.cadence.com/cdnlive/eu/2010/pages/agenda.aspx

Naturally CDNLive will cover *all* aspects of Cadence's technologies and methodologies, including more information on the new EDA360 initiative.  And in general, you can't go wrong by following the whole Functional Verification track.  However, Team Verify can not resist drawing your attention to the following specific papers & techtorials focused on formal and multi-engine ABV.

Tuesday May 4
13:30-15:30, Functional Verification Techtorial Part 1: IEV (Incisive Enterprise Verifier) - Formal Contributions to Verification Closure


Wednesday May 5
12:00-12:30, FV04: Verification of MSP430 uController clock & power FSM-communication using advanced IEV toolbox features
-- presented by Texas Instruments

13:45 - 14:45, FV05&FV06: Cadence's Functional Verification Roadmap
Expectations alert: while this presentation will have a few high-level notes on the IFV & IEV roadmap, consider it more of a roadmap briefing on the whole verification product line.  Please feel free to ask our colleages for a more in-depth, IFV/IEV-specific roadmap review offline.

Thursday May 6
8:45-9:15, FV07: Formal verification of a globally-asynchronous / locally-synchronous (GALS) bridge, using Cadence® Incisive® Formal Verifier (IFV) with a PSL assertion based verification IP (ABVIP) -- presented by STMicroelectronics


11:45-12:15, FV12: Techniques for Applying the Temporal Strength of SystemVerilog Assertions to Specification Level Features -- presented by Freescale Semiconductor


12:15-12:45, FV13: Combining Formal Verification and Simulation to verify a complex LCD controller -- presented by 
STMicroelectronics


Team Verify hopes this summary helps you get the ost out of the show -- and during & after the event please share with us your impressions and feedback.


Happy bug hunting!

Team Verify

(on Twitter: @teamverify)

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.