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Specman-SimVision webinar on April 22 (next week!)

Comments(0)Filed under: Functional Verification, multi-language, e, IEEE 1647, IES-XL, debug, SimVision

We interrupt Corey's excellent "When Less Is More" series to announce a Specman-SimVision webinar next week, April 22 at 10:00AM Pacific time.  In short, if you’ve been using Specview with Specman/e and would like to learn all the key advantages of using the SimVision debug tool, this webinar is for you!

Date:  April 22nd, 2010
Time:  10:00am PDT / 1:00pm EDT
Duration:  60 minutes

Sign Up Today! http://www.secure-register.net/cadence/q2_10_webinars_verification

Who should attend
* Specman/e users who want to learn how to use Specman/e with SimVision

* Incisive Enterprise Simulator-XL (IES-XL) users who have or are planning to upgrade to 9.2 release

* Customers who want to learn more about the SimVision ease-of-use and analysis capabilities

The following topics will be covered in this webinar:

* How digital design and verification engineers can reduce their learning curve by using SimVision as an integrated, unified debug environment for all IEEE standard HVL & HDL languages - e , SystemVerilog, Verilog, VHDL, SystemC, and Verilog-AMS. 

* How a Specman/e user can easily migrate from the Specview debug environment to SimVision

* How easy it is to visualize the extensions of objects in e code

* How to customize the SimVision GUI for Specman users 

* A live demo of SimVision debug, including day-today usage tips like how you can take advantage of multiple ways to set breakpoints/traces on the command line, in the Source Browser, Data Browser, and Design Browser

Some Background on SimVision
Incisive Enterprise Simulator’s SimVision integrated debug environment supports signal-level and transaction-based flows across all IEEE-standard design, testbench, and assertion languages, in addition to concurrent visualization of the hardware, software, and analog domains. SimVision provides a unified simulation and debug environment that allows Enterprise Simulator to manage multiple simulation runs easily and to analyze both design and testbench behavior at any point in the verification process— regardless of the composition.

Throughout the design and verification flow, SimVision provides hardware analysis checks, source browsing, transaction and waveform viewing, and complete code/transaction/assertion coverage analysis.

Application programming interfaces based on industry standards are available at all levels to enable user-defined checks and analysis.

Sign Up Today! http://www.secure-register.net/cadence/q2_10_webinars_verification



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