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DVCon 2010 Rocked!

Comments(0)Filed under: Functional Verification, DAC, OVM, DVcon, uvm, methodology

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010, and I have to say that it was a really good show. This is arguably the most important conference of the year for verification. DAC is lots bigger of course, but DVCon is really focused and there's a core group of colleagues and customers that always make it a fun and simulating event. Although DVCon is still officially the "Design & Verification Conference & Exhibition" every year it looks more and more as if the first ampersand is living on borrowed time.

Cadence and our customers had an especially active presence at DVCon this year, plus I always like to check out what our competitors and their customers are doing, so I couldn't possibly attend every session I wanted. I was really impressed with the technical papers that I did see, especially talks from Doulos on connecting SystemVerilog withC/C++/SystemC and on asynchronous assertions. They have a knack for presentating complex topics in a way that works even for those of us who no longer think about simulation timewheels on a daily basis.

The panels were generally lively, with some pithy comments that I (and others) tweeted in real time. I was really pleased with our sponsored lunch and its panel on debug. It was great that our CEO Lip-Bu Tan made his DVCon debut with a well-attended keynote address. Finally, I was just delighted with the pervasive OVM-related content -- our lunch, the UVM update at the  Accellera lunch, exhibition floor demos, three tutorials, and at least five technical talks including the Best Paper award. It's only a day after the closing session and I'm already looking forward to next year!

Tom A.

The truth is out there...sometimes it's in a blog.   


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