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DVCon: Showcasing The Cadence Passion For Verification Excellence

Comments(0)Filed under: Functional Verification, Low Power, OVM, SystemVerilog, IES, SystemC, e, DVcon, Incisive, ABV, SimVision, Mixed Signal, uvm

Yeah, I know I'm a marketing guy but I really like this stuff!  For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation.  For all of the details, visit our DVCon events page.  Highlighted below are two of the items that I think will be of special interest.

Tutorial: OVM Advanced Topics

With UVM based on OVM, this is a must see.  We will start by describing the latest on OVM for multiple languages -- a requirement voiced by many users for UVM.  The tutorial will then get into the guts of the OVM Low-power methodology, OVM for Assertion Based Verification, and OVM for Acceleration. If you are an OVM user today, this will show you what's coming.  If you are a VMM user, it will show you what you'll be getting as you move to the UVM.

Panel: OVM Found the Bugs, Now How Do We Debug Them Faster?

As our technical team travels the world, we hear time and time again that debugging complex environments is becoming a huge challenge.  This panel will dive into real-world debug challenges users face and we'll be debating the approaches and methodology to address them.  Since this is really a state-of-the-art discussion, the panel will include representatives from Cadence, SpringSoft, the verification user community.

People Make DVCon Great

The biggest thing that makes DVCon so special is that it attracts the best people in our vibrant community. Our contribution this year includes a number of our lead technologists delivering papers and demos as well as the keynote address.  See us in our booth, tutorials, papers, and panels or just stop us in the hall to talk.  If there is one thing that binds us all it is the passion for verification excellence.

 =Adam Sheriblog


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